Question about Quartus Compilation

[Altera_Forum]

Hi everyone 

I am working on a FPGA project using Stratix ii family. When compiling my project, the software automatically using DSP block to map some parts of the project. Now I do not want the these blocks, I only want using the registers and LUTs to cover the whole project. Is there any methods to ban the using of the DSP Blocks? maybe in settings?  Thanks!

[Altera_Forum]

What are the reasons for this? the DSP blocks give superior performance over logic generated multipliers. 

 In assignments -> settings -> Analysis and synthesis settings -> more settings -> auto DSP block replacement   Set to off and see if this helps.

[Altera_Forum]

You also might want to set "maximum DSP block usage" to 0.

[Altera_Forum]

--- Quote Start ---  You also might want to set "maximum DSP block usage" to 0.  --- Quote End ---   Thanks Tricky， I followed your step turning the "Auto DSP Block Replacement" to off and "Maximun DSP Block Usage" to zero, but it doesn't work. The compilation still used the DSP BLOCK. Did I miss anything？

[Altera_Forum]

How are the multipliers generated, are they inferred or from the megawizard? 

You didnt explain why you dont want to use the DSP blocks.

[Altera_Forum]

I think the multipliers are generated by the megawizard cause I used a lot of Arithmetic IP in megawizard such as ALTFP_DIV, ALTFP_EXP and so on. 

As I mentioned in another thread(which is replied by you.Thanks again Tricky), I just want to compare two Algorithm's hardware consumption. Because one of them,when I do compilation, does not consume DSP block, while the other one does. Then I think is there any method to ban the DSP block when compilation,only to use the register and LUT.

[Altera_Forum]

That doesnt really make much sense. The other design obviously uses components that are not suitable for a DSP block. This one does, which is a good thing. DSP blocks are there to be used. Comparing logic for logic is not really that helpful. 

 Just say that the first design uses 0 DSPs and this one uses N.

[Altera_Forum]

--- Quote Start ---  That doesnt really make much sense. The other design obviously uses components that are not suitable for a DSP block. This one does, which is a good thing. DSP blocks are there to be used. Comparing logic for logic is not really that helpful.  Just say that the first design uses 0 DSPs and this one uses N.  --- Quote End ---    Thanks Tricky Now here comes another problem, the Compilation says the number of DSP blocks the project needs is much larger than the FPGA core has. what shall I do now?

[Altera_Forum]

The only options I know of are: 

1. Use a bigger device. 2. Modify your algorithm.  Are you sure you havent accidently set the limits of the DSP blocks to fewer than the device has, having played with the settings.

[Altera_Forum]

--- Quote Start ---  The only options I know of are: 1. Use a bigger device. 2. Modify your algorithm.  Are you sure you havent accidently set the limits of the DSP blocks to fewer than the device has, having played with the settings.  --- Quote End ---    I use the default setting.  Then why just the Compilation use other Hardware instead of the DSP when the DSP resource cant fit the design?