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Hi there,
I'm confused about what the Synthesis and Fitter process do. Synthesis converts the HDL codes into gate-level netlist and Fitter is the step which maps the netlist to the LUT or register in the FPGA. Am I right? If so, when I only do synthesis step, why the report also shows the Resources my program cost. Since the netlist have not been mapped to the FPGA,how does the software know the LUT's cost If not, could someone explain these two steps' differences to me? Thanks a lot!Link Copied
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Yes you are nearly right.
Quartus synthesis shows you a report of an estimation of logic resources needed by your design. The fitter/mapper will show the TRUE resources employed. The fitter targets a specified device (EP2C8...).- Mark as New
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--- Quote Start --- Yes you are nearly right. Quartus synthesis shows you a report of an estimation of logic resources needed by your design. The synthesis doesn't care of target device (I think). The fitter/mapper will show the TRUE resources employed. The fitter targets a specified device (EP2C8...). --- Quote End --- Thank for you reply That is to say, the Synthesis process in Quartus also does the "mapping" job (say some mapping algorithm calculate the LUT ......) ?
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Synthesis translates the RTL to FPGA resources, and is device specific. So, for example, the Cyclone IV has 4-input LUTs, so it will map to that, while Cyclone V has ALMs(Adaptive Logic Modules) and it will map to those. The fitter takes those resources and places them in the FPGA, optimizing for the best timing and routability(and other things, but those are the main two). Synthesis can give a pretty accurate estimate, but the fitter will give ideal. For Cyclone IV, it's straightforward and easy to understand. The Adaptive Logic Module is more complicated because it is adaptive, and therefore synthesis can target different size LUTs and the fitter can pack them together differently, so there's some variation, but it shouldn't be too large.

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