I am a very new user to verilog hdl and unfortunately I don't use it as often so I have to re-learn when I do. I have a simple application where I need to generate a pulse with a duration of 50nS on either the falling edge or rising edge of another signal input and was wondering as to how to approach this in a simple verily statement. Any help would be greatly appreciated. BTW I will be using a 20 or 50 MHz master clock for this device and most likely I will be using a CPLD type device like the MAX3000
