Questions about the Quartus II simulator

[Altera_Forum]

I do most of my simulation in ModelSim, but for smaller designs or quick functional simulations, I really like the convenience of the Quartus II simulator. I do have two questions though: 

 1) Is it possible to simulate entities in my project that are not the top-level entity? Right now, whenever I create a new vwf file, and look for pins on the node-finder, I only see those for the top-level entity. Is there anywhere I can specify that I wish to simulate one of the lower-entities in the design?  2) If my entity has multiple architectures, is there any way to specify which of the architectures I wish to be used for simulation? In ModelSim, I add a line to my testbench such as:  for all : divider use WORK.divider (sequential)  Is there any similar setting for the Quartus II simulator?  Any help on these questions would be greatly appreciated.

[Altera_Forum]

--- Quote Start ---  I do most of my simulation in ModelSim, but for smaller designs or quick functional simulations, I really like the convenience of the Quartus II simulator. I do have two questions though:  1) Is it possible to simulate entities in my project that are not the top-level entity? Right now, whenever I create a new vwf file, and look for pins on the node-finder, I only see those for the top-level entity. Is there anywhere I can specify that I wish to simulate one of the lower-entities in the design?  2) If my entity has multiple architectures, is there any way to specify which of the architectures I wish to be used for simulation? In ModelSim, I add a line to my testbench such as:  for all : divider use WORK.divider (sequential)  Is there any similar setting for the Quartus II simulator?  Any help on these questions would be greatly appreciated.  --- Quote End ---    Hi,  first of all, are aware that the simulator is discontinued. It will be removed with the next Quartus version?  For lower level enties you should find nodes and registers.  I'm not a VHDL expert, I'm not sure how Quartus supports configurations.  Kind regards  GPK

[Altera_Forum]

Hello, mkelner149, 

 Sorry, I just want to ask you a question about how to use Modelsim for SOPC builder system; currently I am really stuck into some Modelsim simulation for quite a long time. Here are the details, and I really wish you could spare some time look at it. That will be greatly appreciated!  I first created an FIR and an FFT using MegaWizard Plug-In Manager. Then the following hdl files are created:   fir_comp_ast.vhd  fir_comp_st.v  tb_fir_comp.vhd  fir_com.vhd  my_fft_tb.v  my_fft_tb.vhd  my_fft_syn.v  my_fft.vhd   Then I connected the FIR and FFT in SOPC builder, between them I put a Dual Clock FIFO, then the following hdl files are created:    fir_comp_0.vhd  dc_fifo_0.v  my_fft_0.vhd  fir_fft_two_sopc.vhd (fir_fft_two_sopc is the name of my sopc system)  fir_fft_two_sopc_inst.vhd  fir_fft_two.vhd (instantiation of my SOPC system)   At this moment, I tried to add every hdl files inside the Modelsim and compile them; I have even added some vho files (maybe they are not necessary). The testbench I used is obtained from the Quartus II, in which I drew a waveform and then exported it as .vht file.   However modelsim has given some compilation errors as follows:    fir_comp_ast.vhd failed with 1 errors:   ** Error: D:/FYP_extra/fir_fft/fir_fft_two/fir_comp_ast.vhd(32): Library auk_dspip_lib not found. ** Error: D:/FYP_extra/fir_fft/fir_fft_two/fir_comp_ast.vhd(33): (vcom-1136) Unknown identifier "auk_dspip_lib". ** Error: D:/FYP_extra/fir_fft/fir_fft_two/fir_comp_ast.vhd(36): VHDL Compiler exiting  compile of fir_comp_ast.vhd failed with 1 errors.  ** Error: D:/FYP_extra/fir_fft/fir_fft_two/fir_compiler-library/auk_dspip_lib_pkg_fir_90.vhd(1): near "<byte 0x8b>": illegal character found in source ** Error: D:/FYP_extra/fir_fft/fir_fft_two/fir_compiler-library/auk_dspip_lib_pkg_fir_90.vhd(1): near "<byte 0x13>": illegal character found in source ** Error: D:/FYP_extra/fir_fft/fir_fft_two/fir_compiler-library/auk_dspip_lib_pkg_fir_90.vhd(1): near "<byte 0x9c>": illegal character found in source ** Error: D:/FYP_extra/fir_fft/fir_fft_two/fir_compiler-library/auk_dspip_lib_pkg_fir_90.vhd(1): VHDL Compiler exiting  # compile of my_fft.vhd failed with 1 errors. ** Error: D:/FYP_extra/fir_fft/fir_fft_two/my_fft.vhd(34): Library fft_lib not found. ** Error: D:/FYP_extra/fir_fft/fir_fft_two/my_fft.vhd(35): (vcom-1136) Unknown identifier "fft_lib". ** Error: D:/FYP_extra/fir_fft/fir_fft_two/my_fft.vhd(37): VHDL Compiler exiting    It seems that I have added some unnecessary files or missed some compulsory files? So, could you please advice on which files are necessary for my modelsim project?  Thank you so much for your patience!  Best regards