Questions from a lab exercise.

[Altera_Forum]

Questions from a lab exercise. 

 Hi all, I am quite new with VHDL language and Quartus, just started to learn from 3 months ago. I got a lab exercise like this. I have been doing that for 2 weeks now, so tiring. The teachers are useless, go and ask them, they just gave me some silly answers. The deadline is in next week, just a lab exercise but it seems very hard for me to do. Ok. So the lab is like this simulation & synthesis of hc11 core aim: To integrate an existing HC11 VHDL core memory and I/O, so that it can be fully synthesized and will execute a simple fragment of compiled C code. introduction: We will start with a freely available HC11 processor core from Green Mountain website ( Google keyword "GM HC11 core") You can download all of the initial files from there. exercise:

• Access the two files hc11rtl.vhd and syncore.vhd. Use the Quartus II environment to encapsulate the code as a schematic component.

• Create a new project and add a top-level schematic block diagram. i.e. import the component from point 1. above into the schematic page.

• Connect a RAM block to the HC11 symbol. Write a VHDL version of the HC11 port structure (DDR and I/O registers). Encapsulate the port circuit and instantiate it into your design—as Port A. Make sure you understand how memory and ports are mapped in the HC11 (i.e. memory mapped 
• Once you have connected the respective VHDL blocks together, create a small fragment of C code and compile it using appropriate tools (you will find CodeWarrior on the network). Transfer it to the program memory and simulate it running on the core 
• Finally, download the compiled file to an Altera DE-1 board and run it. The code will need to do something obvious, like flash a LED sequence, or drive the 7-segment displays, via connections to the port A.

 And what I have done so far  I downloaded the HC11 core from GM website, I have finished the first section, use syncore.vhd create a symbol file ( The CPU). In the packet downloaded from the GM website, we have RAM,ROM, clock…., but my teacher said don’t use that, just make a simple system, so I used only the core from the packet  I also wrote the code for the port here and add it into a schematic diagram. I created a RAM block from mega wizard according to the size of the RAM on chip of HC11(512 words x 8 bits).  To map the addresses for RAM and PORTA here I created a decoder block, and I intended to define the address for the RAM is in the range from 0000 – 01FF ( like in the HC11 datasheet), and the address for PORTA is (0x0200), DDRA (0x2001).   The clock here I used the clock signal on DE1 board 27Mhz divided by 9 to get 3Mhz, and connect it to E clock of the CPU. There are a lot of points I still don’t understand, like pin rw of the CPU, how to connect the data in and data out into data bus(here I used the mux), but I dunno is it correct? The input of the mux, the sel(1-0) where will we connect those.   And I am not sure that all the things I have done so far is totally wrong.Hic:confused: And after finish the hardware and burn the program into the board. How to write the C code? How to add it into FPGA on board? The only thing I need to do to make the C code to flash a LED on board.   Thanks for watching my long question, if anybody can help me or suggest the solutions, I really appreciate that. I will post here all the code I have done also

[Altera_Forum]

Just update what I just tried. I feel I understand more than before, but still dunno what to do next. I hate my teachers now. Haha 

 What I added here is   + Take rw signal from CPU, if rw = 1 that means write, and rw =0 that means read.  + The mux here to control the data bus  + The encoder to decide which signal receive commands from CPU( I think…:D)  + So according to the encoder, we will get   If we wanna read from RAM, we choose address for RAM ( Ram_en will be 1), Sel =00; the data from RAM will connect to the data bus( I think)   The same for PORT A, Sel =01 when Port_En =1    Good news is I can compile it without any errors. Haha. Thanx for seeing my ques.