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RISC 16 sequential implementation in vhdl

Altera_Forum
Honored Contributor II
‎12-18-2015 10:03 PM
3,816 Views

I am working now on implementing a 16 bit RISC CPU in VHDL, the instruction set consists of 8 instructions 16 bits each. 

the architecture of the data path and instruction flow is attached , i need your help how to start implementation? could you give me examples for source codes like this architectur
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Altera_Forum
Honored Contributor II
‎12-24-2015 09:43 AM
2,698 Views

Hi, 

 

actually I do not understand what you really want to do and how you want us to help you. What I understand is that you want to code your own CPU in VHDL. I can point you to a general idea of a processor, which is part of the Altera University Program Labs. You find the instruction of that Lab here: https://www.altera.com/support/training/university/materials-lab-exercises.html#digital-logic-exercises 

 

The labs are called: Lab 9 - A Simple Processor and Lab 10 - An Enhanced Processor. 

 

I hope that helps, but again I am not sure what you are doing.
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