ROM in VHDL

[Altera_Forum]

Hi All,  

 I'm using DE2 FPGA to play something from a microphone pass it through DE2, do some filtering and play it back through de2. So far, I was successful on playing mic back from speakers.  Now I'm trying to apply a filter to my samples coming from the mic. I have some ideas on how it suppose to work, but I'm not familiar on how to use the ROM for storing the data and reading it back.  I need to store some samples coming from mic into the rom, say like 4 samples, then I'm going to apply an FIR filter and pass those data back to another array, play it back when I got 4 samples on my second array. I basically need a counter to go through these arrays.  Here's what I got for this part so far, it's not complete and it has syntax errors, I'm not really sure how to go on from here. I'm not sure what addresses to choose, and how to use my counter to move through these addresses.   ARCHITECTURE Behavorial OF sram IS  signal count : std_logic;   begin counting : process(clk, adc_full) begin count <= '0'; if (rising_edge(clk)) then if (adc_full = '1') then count <= count + '1'; end if; end if; end process;   type rom_type is array (0 to 15) of std_logic_vector(7 downto 0);  constant ADC_array : rom_type :=  ( 0 => "00010000", 1 => "00010001", 2 => "00010010", 3 => "00010011", 4 => "00010100", 5 => "00010101", 6 => "00010110", 7 => "00010111");  begin process (count) begin case count is when "0000" => data <= ADC_array(0); when "0001" => data <= ADC_array(1); when "0010" => data <= ADC_array(2); when "0011" => data <= ADC_array(3); when "0100" => data <= ADC_array(4); when "0101" => data <= ADC_array(5); when "0110" => data <= ADC_array(6); when "0111" => data <= ADC_array(7); when others => data <= "00000000"; end case; end process;

[Altera_Forum]

Do yo want to do the work or just infer rom(for just few samples)? 

I suggest you don't worry about whether a rom is inferred or not(leave that to the tool for now). Note your data is constant inserted by you not ADC and so contradicts what you say.   ARCHITECTURE Behavorial OF ... IS signal count : integer range 0 to 7 := 0; type my_type is array (0 to 7) of std_logic_vector(7 downto 0); constant ADC_array : my_type := -- { or (, not sure of syntax (0 => "00010000", 1 => "00010001", 2 => "00010010", 3 => "00010011", 4 => "00010100", 5 => "00010101", 6 => "00010110", 7 => "00010111"); begin process(clk) begin if (rising_edge(clk)) then if (adc_full = '1') then count <= count + 1; end if; data <= ADC_array(count); end if; end process; end architecture;

[Altera_Forum]

Why did you use : 

data <= ADC_array(count); ? Don't we need to write whatever data is coming in into the array? How do i do that? When i tried  ADC_array(count) <= data; (data is of mode IN), i get an error saying "ADC_array is not a signal")

[Altera_Forum]

If you want a ROM, then you cannot write any data to it. You cant write data into it in the code because ADC_array was declared constant, so it cannot be modified. You'll have to make it a signal (and therefore it wont be a rom anymore.)

[Altera_Forum]

--- Quote Start ---  If you want a ROM, then you cannot write any data to it. You cant write data into it in the code because ADC_array was declared constant, so it cannot be modified. You'll have to make it a signal (and therefore it wont be a rom anymore.)  --- Quote End ---    Thanks for the prompt response.  I don't think I can use signals to store the samples though, right? Cause I need to store my data coming from the microphone into a memory, say like 8 samples of 32 bits. Then Call each sample, apply a filter and then read them back to the speakers when the specified control signals in the audio codec is set to high.

[Altera_Forum]

whats wrong with signals? 

Signals can store values, create memories and other things. It is how you use them that makes the logic, not the other way round.

[Altera_Forum]

--- Quote Start ---  Thanks for the prompt response.  I don't think I can use signals to store the samples though, right? Cause I need to store my data coming from the microphone into a memory, say like 8 samples of 32 bits. Then Call each sample, apply a filter and then read them back to the speakers when the specified control signals in the audio codec is set to high.  --- Quote End ---    Okay, how does this look like? I added the read part a well.  library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.all;   entity sram is  Port   (clk, Reset, run : IN std_logic;  adc_full, data_over : IN std_logic;  data : IN std_logic_vector (7 downto 0);  ADCout : OUT std_logic_vector(7 downto 0));   end sram;   ARCHITECTURE Behavorial OF sram IS    signal adccount, datacount : integer range 0 to 7 := 0;   --CONSTANT word_limit : integer := 15; type mem_type is array (0 to 7) of std_logic_vector(7 downto 0);   signal ADC_array : mem_type :=  ( 0 => "00010000",  1 => "00010001",  2 => "00010010",  3 => "00010011",  4 => "00010100",  5 => "00010101",  6 => "00010110",  7 => "00010111"); BEGIN   process(clk)  begin if (Reset = '1') then  adccount <= 0; elsif (rising_edge(clk)) then  if (adc_full = '1') then  adccount <= adccount + 1;  end if;  ADC_array(adccount) <= data ; end if; if (adccount = 8) then adccount <= 0; end if; --read the data  datacount <= 1; if (rising_edge(clk)) then  if (data_over = '1') then  datacount <= datacount + 1;  end if;  ADCout <= ADC_array(datacount); end if; if (datacount = 8) then datacount <= 0; end if;   end process;     END Behavorial;

[Altera_Forum]

And another question, If I want to change my data to 32 bits, instead of 8 bits, how should change this part?  

 type mem_type is array (0 to 7) of std_logic_vector(7 downto 0);   signal ADC_array : mem_type :=  ( 0 => "00010000", 1 => "00010001", 2 => "00010010", 3 => "00010011", 4 => "00010100", 5 => "00010101", 6 => "00010110", 7 => "00010111");  Also, if I need to read these data back to do some operation on them, can I just simply get my output I read from my memory and connect it to my other entity that I'm doing that specific operation? Or do I need to call every sample, if that make any sense. Since I have 8 samples, and I need to do this on each sample, am I gonna get one sample at a time? or all of them together? I have a very unclear view on how to deal with these output I'm reading from the array.

[Altera_Forum]

--- Quote Start ---  And another question, If I want to change my data to 32 bits, instead of 8 bits, how should change this part?   type mem_type is array (0 to 7) of std_logic_vector(7 downto 0);   --- Quote End ---    type mem_type is array (0 to 7) of std_logic_vector(31 downto 0);    --- Quote Start ---   Also, if I need to read these data back to do some operation on them, can I just simply get my output I read from my memory and connect it to my other entity that I'm doing that specific operation? Or do I need to call every sample, if that make any sense. Since I have 8 samples, and I need to do this on each sample, am I gonna get one sample at a time? or all of them together? I have a very unclear view on how to deal with these output I'm reading from the array.  --- Quote End ---    Forget the code. Step away from the code. Now get out some paper and draw the circuit you're trying to achieve. If you cannot do this, you should not be writing VHDL or Verilog. VHDL is NOT like writing C. if you dont understand the circuit you're creating, you cannot expect to write VHDL.