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Altera_Forum
Honored Contributor I
951 Views

RTL module+OpenCL-top file synth .v from .cl can't find clock,resetn,AvalonST signals

Hi, 

 

I'm trying to get a customised FFT1D example working. Basically it is the same as the example fft1d from the library, except I am adding in an RTL module which executes an XOR function. The idea is that fft1d runs normally, but also calls a function XOR which maps to the RTL module. This serves no real application - I'm doing this simply to learn the programming flow for combined OpenCL/RTL functionality.  

 

I build the RTL library etc, and go to compile the highest level .cl file (fft1d.cl). Everything compiles fine, and it gets past the First Stage Compilation Successfully, but then fails with: 'Error: Compiler Error, unable to generate hardware.'. 

 

I went digging through the log and eventually came upon 6 errors: Certain signals that are in my .xml file are missing from the synthesised fft1d.v file. (I didn't write the .v file, I assume the compilation process generates this from the .cl) In any case, the log has this:  

 

Error (13305): Verilog HDL error at fft1d.v(8041): can't find port "clock" File: <my_file_path> 

Error (13305): Verilog HDL error at fft1d.v(8042): can't find port "resetn" File: <my_file_path> 

Error (13305): Verilog HDL error at fft1d.v(8043): can't find port "m_ready_in" File: <my_file_path> 

Error (13305): Verilog HDL error at fft1d.v(8044): can't find port "m_valid_in" File: <my_file_path> 

Error (13305): Verilog HDL error at fft1d.v(8045): can't find port "m_ready_out" File: <my_file_path> 

Error (13305): Verilog HDL error at fft1d.v(8046): can't find port "m_valid_out" File: <my_file_path> 

 

From the Programming Guide, section 12, these signals are all required for Avalon ST for RTL module to be included. I assumed that the compilation process took care of everything else, provided I had these in my .xml file. What have I missed? 

 

Much thanks for your time. 

 

ap29
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2 Replies
Altera_Forum
Honored Contributor I
48 Views

I have never personally done this, but Altera has a library design example here: 

 

https://www.altera.com/support/support-resources/design-examples/design-software/opencl/library-desi... 

 

You can take a look at the example and see if you can fix the problem by imitating what is done by Altera.
Altera_Forum
Honored Contributor I
48 Views

 

--- Quote Start ---  

I have never personally done this, but Altera has a library design example here: 

 

https://www.altera.com/support/support-resources/design-examples/design-software/opencl/library-desi... 

 

You can take a look at the example and see if you can fix the problem by imitating what is done by Altera. 

--- Quote End ---  

 

 

Hi HRZ, 

 

I've looked at the example - actually the code I'm trying to get running is a combination of fft1d example and library2 example. I found my issue last night actually: 

 

The XML file needs to include clock, resetn, and the 4 AvalonST signals. ADDITIONALLY (which I did not initially have), these 6 extra signals need to explicitly be included in your RTL module .vhd or .v. I think the synthesiser generates the same signals at a higher level RTL module (i.e the fft1d.cl module) and then connects them straight to my RTL module. Because my module did not have these signals, they could not be routed anywhere, which is why the .log was complaining about these signals in the synthesised fft1d.v file.  

 

In any case, my kernel compiled - thanks for the help. 

 

ap29