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Valued Contributor III
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RTL module crashes computer

Hi,  

 

I have a purely combinatorial RTL module as part of my OpenCL pipeline. The design compiles without problems or warnings. However, when executing the program, it first stalls for a few minutes, then the entire computer hangs and requires a manual restart. I can't make sense of this because: 

 

- Simulating the verilog itself works. 

- The design has no internal states and it's stall free with a fixed (0) latency. 

- Just using a simpler (but also combinatorial) design without touching any of the other code does not show the problem. 

- Status flags iready/oready/ivalid/ovalid are not used (just routed through) 

- The output of the RTL module just gets transferred back to the host (no further computation depends on it).  

 

I'm using the 16.1 SDK with the DE5a-net board. Any suggestions on how to debug this would be appreciated! 

 

Thanks,  

Hanno
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