RTL sequence to VHDL translation

Altera_Forum · ‎06-21-2016

How would i place this RTL sequence and convert it into VHDL

input:clk,mr,x,dat[6]

output:rdy,err,resa[3].resb[3]

registers;rega[3]. regb[3]

sequence:

0. regb<=000

1. rega <=dat [5..3]; =>(x=0)/(1)

2.=> (dat [2..0] = 000)/(5)

3. => (dat[5..3}> dat[2..0]/(6)

4. rdy =1; resa =rega; resb= regb; =>(4)

5. err =1; >=(5)

6.regb <=regb +1; rega<=rega - dat[2..0]; => (4)

control reset 0

Altera_Forum · ‎06-21-2016

How much VHDL do you know? Try yourself first, then ask us to help on the points you are stuck on.

Altera_Forum · ‎06-22-2016

Hi there, I know alittle to get me through RTL to VHDL conversion.

The question i have is in regards to dat[6], is that written as data: In bit_vector (6 downto 0);

For resa[3] and resb [3], is it related in this form:

Architecture RTL_sequence to VHDL_translation is

Port (resa , resb: OUT_bit (3 downto 0);

or in

SIGNAL resa: bit_vector (3 downto 0);

resb: bit_vector (3 downto 0);

Altera_Forum · ‎06-22-2016

your questions are not clear - have you worked your way through a VHDL tutorial?