Random number generation and indexing into RAM/ROM block

[Altera_Forum]

Altera Gurus, 

 I am developing a random pulse generator based on certain external inputs. The pulse generator will be implemented on a Cyclone III device and coded in VHDL using Quartus. The amplitude of these pulses are controlled by an external amplitude spectra. This will be stored in .mif files which will be used to initialize ROM/RAM blocks. I have implemented a 2^16 pseudo-random number generator based on the LFSR method. These random numbers map to a certain amplitude. These mappings are stored in the .mif file. The mapping is many-to-one; many random numbers map to the same amplitude. An example is shown below to explain the logic:  x[0] = 1 x[1] = 5 x[2] = 10  In my code, if I generate a random number between 1 and 5, then my amplitude will be 1. Similarly if a random number is generated between 5 and 10, the amplitude will be 2. So the amplitude is the index+1. I am having trouble implementing this logic in VHDL. It's not a true ROM/RAM in the sense that the "address" being input to the ROM/RAM block is not the index, but is used to determine the index. For now I have for-loop which basically runs through the entire array, compares the random number to the values in the array, and outputs the index. However, Quartus will no longer synthesize a ROM/RAM block with this logic. Plus I would have to declare a massive constant array (256 values) to implement this since I didn't see a way to initialize a constant array from a .mif file.   Any ideas/thoughts as to how I can implement this logic by using RAM/ROM blocks and for-loops?  I've drawn a crude picture of what I want to implement.  https://www.alteraforum.com/forum/attachment.php?attachmentid=9328

[Altera_Forum]

Hi , 

 "It's not a true ROM/RAM in the sense that the "address" being input to the ROM/RAM block is not the index, but is used to determine the index."  So according to your diagram , what is 'Pseudo-Random Number Generator' generating a random address for a random location on ROM/RAM ?  "For now I have for-loop which basically runs through the entire array, compares the random number to the values in the array, and outputs the index. However"  Entire array i.e the ROM/RAM ? is this logic a wrapper with ROM/RAM as a component inside it ?  Ahmed Asim Ghouri  Embedded Strings inc Website : www.emstrings.com Email : support@emstrings.com

[Altera_Forum]

Yes you cannot initialize a array which is defined in vhdl as type array ( 0 to 15) of std_logic_vector( 15 down to 0 ), but you can initialize a ROM/RAM with .mif file , i have done with .mif generated using Matlab .

[Altera_Forum]

Ahmed, 

The number generator outputs a random number that is then used to determine the address into the ROM/RAM. So in my example, if the random number 5 is output by the PRNG, this value is read in by the RAM/ROM block, a for-loop is run to determine which index corresponds to this number, and the output of the ROM/RAM block is the index. I made a slight mistake in the diagram-the amplitude out is NOT an input to the PRNG, it is used by a different block of code. The for-loop logic currently resides in the ROM/RAM block. It is not a wrapper at the moment. The loop requires that I declare the entire array as a constant. I cannot loop through an array that I read in via a .mif file. So this is why the synthesizer does not instantiate a ROM/RAM block. I call it a ROM block in the diagram, but due to this logic it is not implemented as such. This is where I'm having trouble with the logic.     --- Quote Start ---  Hi ,  "It's not a true ROM/RAM in the sense that the "address" being input to the ROM/RAM block is not the index, but is used to determine the index."  So according to your diagram , what is 'Pseudo-Random Number Generator' generating a random address for a random location on ROM/RAM ?  "For now I have for-loop which basically runs through the entire array, compares the random number to the values in the array, and outputs the index. However"  Entire array i.e the ROM/RAM ? is this logic a wrapper with ROM/RAM as a component inside it ?  Ahmed Asim Ghouri  Embedded Strings inc Website : www.emstrings.com Email : support@emstrings.com  --- Quote End ---  

[Altera_Forum]

--- Quote Start ---  Yes you cannot initialize a array which is defined in vhdl as type array ( 0 to 15) of std_logic_vector( 15 down to 0 ), but you can initialize a ROM/RAM with .mif file , i have done with .mif generated using Matlab .  --- Quote End ---    You can easily initialise a rom with a function or a constant, no matter what the type declaration. Check the altera coding guidelines.   I don't think I fully understand the ops problem. It sounds like all you need is a rom that is setup using a vhdl function.

[Altera_Forum]

"Yes you cannot initialize a array which is defined in vhdl as type array ( 0 to 15) of std_logic_vector( 15 down to 0 )" 

 I meant with a .mif file   Ahmed Asim Ghouri Embedded Strings inc Website : www.emstrings.com Email : support@emstrings.com