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Hello,
I have a design based on the 144 pin EP3C25. I programmed a NIOS II processor with external SRAM connected to the FPGA but for this I need more than 30-pins. In order to reduce this amount I found and EDN article in which is descibed how to multiplex the data-lines with the lower address-lines. I have attached this article (Look for: SDRAM interface slashes pin count). Is there someone who could help me to implement this solution in the altera sdram.vhd which is generated by the MegaWizard Plug-In Manager. I tried to understand how the SDRAM-interface is implemented with sdram.vhd but because i am beginner using FPGA's it is still too complicated for me at this moment. Thank you and best regards, WamorLink Copied
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