Remotely resetting FPGA via JTAG ?

[Altera_Forum]

The Quartus II programmer automatically releases the FPGA from reset after downloading an image into it (or a flash device connected to it). 

 I would like to be able to reset the FPGA without having to download an image, as I use a remote JTAG connection.    Now I have to: a) Download an image just to reset the FPGA, or b) Cross the building to get to the hardware and reset it manually.   Both ways take too much time.   Who knows how to reset an FPGA from the PC using the Altera tools?

[Altera_Forum]

I noticed there are 2 old thread on this issue: 

 http://www.alteraforum.com/forum/showthread.php?t=16487 [zero replies]   and   http://www.alteraforum.com/forum/showthread.php?t=18882 [unsolved]   I find it hard to believe there is no solution for such a trivial problem.   All I need is to reset / reinitialize the FPGA remotely.    So far, I haven't found a way to do that.

[Altera_Forum]

Designers can reset the fpga remotely using soft reset, obviously provided you have software control. Otherwise I suggest two options: 

 1) use in-system memory editor to write to a register which is hardwired to be ORed with your master reset.   2) I normally don't need reset as i include user power up reset to follow the fpga reset release as the latter is unreliable at release.

[Altera_Forum]

It's definitely possible, but as kaz hints it's more system dependent than anything else. For instance, you could have a standard I/O pin on your FPGA that drives nConfig. Connecting that pin to an output PIO in SOPC Builder and then IOWRing to it would trigger an FPGA reset. 

 Similarly, the altremote_update megafunction does not require that an image be downloaded prior to reset. You just have to write to the appropriate registers in the IP to trigger a reset to either a factory or user image.  So, definitely do-able, but how it's done is system dependent.  Cheers,  -slacker

[Altera_Forum]

I used to hack my system reset by adding in another 'soft reset' case by instantiating the 'constant' megafunction in my design and parameterizing it to support in-system memory editing. It basically hooks up a lookup table to JTAG so that you can flip the contents between '0' and '1'. Then you connect to a live system using the in-system memory editor and modify the value.

[Altera_Forum]

You most likely have noticed, that the Altera Programmer tool has an option to reconfigure the FPGA after e.g. downloading a serial flash image. I didn't yet check how it's done, but I remember to have heard about generic boundary scan commands used for this action. Otherwise there must be an Altera specfic programming instruction for reconfiguration.