Resource origin locations for ID Logic Locked partitions?

[Altera_Forum]

I've just upgraded from Q2 v7.1 to Q2 v7.2 SP3. The project I just completed was a Bottom Up ID design into a Stratix 2 where the Project Leader wanted me to remain in v7.1 until completed. The design I'm now working on is a modification of the previous design, which means to still use the Bottom Up Methodology, but to move up to Q2 v7.2. Today I ran into my first problem: 

In v7.1 one could still use the old FloorPlanner tool to view the insides of the Stratix 2 device. The best thing about this was that one could get the origin information on LABS and other resources in the device. This was perfect for choosing an origin position for an ID Partition's Logic Lock Region so that it wouldn't overlap or otherwise conflict with other Partitions in the Top Level of the design.  In v7.2 however the old FloorPlanner tool nolonger functions for Stratix 2 devices. When calling it up it is stated to use ChipPlanner instead. But ChipPlanner doesn't display resource origin information without which conflicts arise.  How do I now get that information?  I do see that if I use ChipPlanner and declare an LL Region it will display ITS origin but not those of the surrounding logic. Still not really good enough since non-conflicting placement requires such.  I'm not given the time to convert the project to Top Down if thats one suggestion so please lets not go there on this one. So I repeat...  How do I get that information?  (As an addendum; I've played with ChipPlanner Vs. FloorPlanner before and find the ChipPlanner very very lacking. Does anyone know why they are going to such an incomplete and raw tool?)

[Altera_Forum]

Not sure what you mean by resource origin information. If you mean the LLR location, that should be in the LLR window, which I keep up alongside the Chip Planner. If you just mean generally where logic is, you can edit the layers on the top right and turn on the co-ordinates(it's about halfway down the list), so every lab, memory and DSP block is super-imposed with it's X/Y co-ordinates. It's a little cluttered, so I only turn it on when placing LLRs.  

I used the old floorplanner all the time, and for the most part find I can do the same stuff in the Chip Editor. It didn't make sense to work on two separate tools that did almost identical stuff. I do believe improves are being worked on for the chip planner to make it more intuitive, but don't think it will be any time soon. But again, I've been able to do almost everything I did in the old one(along with many new capabilities).

[Altera_Forum]

What I mean by resource origin location are the X#_Y# for LABS, M512, M4K, etc. that one can get from the old FloorPlanner by just zooming in some and placing the pointer on the upper left corner of any one. I've just tried again looking through the menu selections in ChipPlanner to see how to turn on such information to view and its just not there. 

I use (used) the location information from FloorPlanner to plan the locations of my Incremental Design Partitions in the Bottom Up flow. As far as I can see, when work on designing subpartitions, ChipPlanner leaves one in the dark. (Why?)  I gotta tell you, the more I use ChipPlanner the less I like it. It doesn't jive with the other tools like the PinPlanner, it crashes randomly bringing down the entire Q2 system with it and it doesn't have any of the basic information the FloorPlanner did. (I still have to view ChipPlanner as an unfinished tool that was pushed out too soon.)