Ripple clock going off chip using Timequest

[Altera_Forum]

I am trying to divide down a clock by 1024, yes I know that old chesnut (150KHz) and have no PLLs left. I was just using a counter and picking out bit[9] to act as  

my clock. This clock was then used to clock data out from my fpga and then latch it in the receiving device.  always@(posedge clk or negedge reset_n)  begin  if (!reset_n)  counter <= ‘b 0  else  counter <= counter + 1’b1;  end   always@(posedge clk or negedge reset_n)  begin  if (!reset_n)  div_clk_1024 < = ‘b 0;  else  if (counter[9])   div_clk_1024 <= ‘b 1;  else  div_clk_1024 <= ‘b 0;  end  From Altera’s description, a ripple clock is any clock port driven by the output port of a register. So div_clk_1024 is a ripple clock. My two questions are..  1) If I constrain this properly in timequest and if it passes timing then am I ok? I am aware of the issues with ripple clocks from Brad’s/ Rysc’s and Kaz great documents.  e.g. create_generated_clock -name div_clk_1024 -source [get_pins {phy_pll_i|altpll_component|auto_generated|pll1|clk[0]}] -divide_by 1024 [get_nets { div_clk_1024 }]   2) As is normal for this sort of problem, the recommendation is to use a 1 clk wide clock enable to transfer the data but what happens if you are creating this clock to go off device and you don’t want to be sending the clock enable along for the ride?  I take it the sdc constraint would just be to create another generated clock to go off chip i.e.  create_generated_clock -name div_clk_1024_out -source [get_nets { div_clk_1024 }] [get_ports { div_clk_1024_out}]  Any advice would be gratefully received.  C

[Altera_Forum]

1. As long as it passes timing analysis, then you're ok. 

 2. In such cases, bite the bullet and use a ripple clock. Again, as long as the design passes timing analysis, you're ok.