SATA Power Modes, C code problem

[Altera_Forum]

My issue is I read the value of ADI_DEV_CORE_STATUS it remains as 0x2A, even after I write assert a 1 on bit 22 to enable power mode requests, and i prit out the value directly after the value doesn't change. 

I'm trying send a a request to go to slumber mode,  In the ADI DEV CORE STATUS register,  bit 26 is defined as power mode fail (read only),  bit 25 is defined as Core in sleep (read only),  bit 24 is defined as a power mode request for partial slumber (read/write),  bit 23 is defined as a power mode request for slumber mode(read/write), bit 22 is defined as enables Host Initiated Power Mode requests(read/write), bit 21 is defined as initiates the sending of COMWAKE Burst pattern to wake up from slumber (read/write) bit 5 is defined as Phy-Ready (read only), bit 4 is defined as Reset (read/write), bit 3 is defined as indicates device state machine is in Idle(read only), bits[2:0] are defined as Current interface speed(0h: No connection)(1h:Gen1 rate established)(2:h: Gen 2 rate established)(3h: Gen3 rate established)(other values reserved for future generations)  other values defined in code /*Device Application Status (DevCoreStatus Register 0x002C)*/  DEV_STATUS_SIM = (1 << 31), /*Core in Simulation*/  DEV_STATUS_PM_FAIL = (1 << 26), /*Power Mode Fail*/  DEV_STATUS_CORE_SLEEP = (1 << 25), /*Successful Transition into Sleep Mode*/  DEV_STATUS_PARTIAL_GO = (1 << 24), /*Power Mode Request for Partial Mode*/  DEV_STATUS_SLUMBER_GO = (1 << 23), /*Power Mode Request for Slumber Mode*/  DEV_STATUS_EN_PWDN = (1 << 22), /*Enables Host Initiated Power Mode Requests*/  DEV_STATUS_COMWAKE = (1 << 21), /*Initiates the Sending of COMWAKE Burst Pattern to Allow for Waking up from Slumber*/  DEV_STATUS_PHYRDY = (1 << 5), /*Indicates the Device Core has Achieved a Phy-Ready State*/  DEV_STATUS_RESET = (1 << 4), /*Upon Exit From Reset, Device will Send a COMINIT*/  DEV_STATUS_DEVIDL = (1 << 3), /*Device State Machine is in Idle*/  DEV_STATUS_SPEED_0 = (0x0 << 0), /*0h: No Connection to the Host Established*/  DEV_STATUS_SPEED_1 = (0x1 << 0), /*1h: Gen 1 Communication Established*/  DEV_STATUS_SPEED_2 = (0x2 << 0), /*2h: Gen 2 Communication Established*/  DEV_STATUS_SPEED_3 = (0x3 << 0), /*3h: Gen 3 Communication Established*/  struct DevDesc {  u32 * mmio; //memory mapped io address  u32 qd_cmd; //queued command - doesnt appear to be used yet. guessing active-high 32 bits  u8 phy_rdy; //phy_rdy flag - set by software  u8 spd_allowed; //same as below. doesnt appear to be used yet  u8 cur_lnk_spd; /* 00 -> Not phyrdy, 01 -> Gen1 -> 02 -> Gen2, 03-> Gen3*/  u8 dev_mode; /* DEV_MODE_xxx, eg SATA, SAS, dual */  struct ata_port_operations *ops; //what is this? doesnt appear to be used  };  struct MemDesc {  u32 * non_qd_dev_mem_addr;  u32 non_qd_dev_mem_span;  u32 * qd_dev_mem_addr;  u32 qd_dev_mem_span;  u32 * sg_addr;  u32 sg_span; };  struct MemDesc mem_desc_g = {  .non_qd_dev_mem_addr = (u32*)(DEV_PORT_MEMORY_BASE), //Non-queued command memory. base=0x40000  .non_qd_dev_mem_span = DEV_PORT_MEMORY_SPAN, //65536 bytes - 0x40000:0x4FFFF  .qd_dev_mem_addr = (u32*)(DATA_BUFFER_BASE_ADDRESS), //Queued command buffer. base=0x50000.  .qd_dev_mem_span = DATA_BUFFER_SPAN, //65536 bytes - 0x50000:0x5FFFF  .sg_addr = (u32*)(DEV_SG_MEMORY_BASE), //Scatter-gather list. base=0x60000  .sg_span = DEV_SG_MEMORY_SPAN, //65536 bytes - 0x60000:0x6FFFF };  //System descriptor //Points to components struct Iprop_SysDesc sys_desc_g = {  .dd = &dev_desc, //device core descriptor  .md = &mem_desc_g, //memory structure descriptor };   u32 RegRead32(u32* BaseAddr, u32 Offset) {  u32 temp;  temp = (u32)BaseAddr + Offset;  return *(volatile int *)temp; }  void RegWrite32(u32* BaseAddr, u32 Offset, u32 WriteData) {  u32 temp;  temp = (u32)BaseAddr + Offset;  *(volatile int *)temp = WriteData;  return; }   u32 power_mode_sleep (struct SysDesc * sd) {  rc = RegRead32((u32*)DEV_BUS_SLAVE_BASE, ADI_OFFSET + ADI_DEV_CORE_STATUS);  alt_printf("The value of ADI_DEV_CORE_STATUS is 1.) %x \n", rc); /*Should print out 0x2A, phy-ready, in idle, and Gen2 speed*/  rc = rc & 0xFF3FFFFF;  rc |= DEV_STATUS_EN_PWDN; //DEV_STATUS_EN_PWDN = (1<<22)  RegWrite32((u32*)DEV_BUS_SLAVE_BASE, ADI_OFFSET + ADI_DEV_CORE_STATUS, rc);  read = RegRead32((u32*)DEV_BUS_SLAVE_BASE, ADI_OFFSET + ADI_DEV_CORE_STATUS);  alt_printf("The value of ADI_DEV_CORE_STATUS is 2.) %x \n", read);  rc |= DEV_STATUS_SLUMBER_GO;  RegWrite32((u32*)DEV_BUS_SLAVE_BASE, ADI_OFFSET + ADI_DEV_CORE_STATUS, rc);  read = Iprop_RegRead32((u32*)DEV_BUS_SLAVE_BASE, ADI_OFFSET + ADI_DEV_CORE_STATUS);  alt_printf("The value of ADI_DEV_CORE_STATUS is 3.) %x \n", read);  rc = wait_reg((u32*)(DEV_BUS_SLAVE_BASE + ADI_OFFSET + ADI_DEV_CORE_STATUS),  0x2000000, // only look at bit 25.  0x000000, // if bit-25 == 1, We're core in sleep  1, // wait 1us between register reads  100000); // ~100ms  alt_printf("The value of ADI_DEV_CORE_STATUS is 4.) %x \n", rc); /**/  read = RegRead32((u32*)DEV_BUS_SLAVE_BASE, ADI_OFFSET + ADI_DEV_CORE_STATUS);  alt_printf("The value of ADI_DEV_CORE_STATUS is 5.) %x \n", read);  if ((read & 0x2000000) == DEV_STATUS_CORE_SLEEP)  {  alt_printf("Successfully Transitioned into sleep mode.\n");  }  else if ((read & 0x4000000) == DEV_STATUS_PM_FAIL)  {  alt_printf("Unsuccessful Transition into sleep mode.\n");  }  else  alt_printf("The value of ADI_DEV_CORE_STATUS is 6.) %x \n", rc);  return STATUS_SUCCESS; }