Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15311 Discussions

SCFIFO in LE-mode: empty and full not affected by write/read

Altera_Forum
Honored Contributor I
872 Views

Hi, 

 

I am implementing a small Avalon-ST buffer using the SCFIFO in showahead mode implemented as LEs. I converted my project from Quartus Pro 17.1 to Pro 18.0 and since then I have had problems with the empty/full signals. When I write to the FIFO, the usedw signal is incremented as it should but empty and full don't chance. 

 

In the attached SignalTap screenshot I am writing my second two-word packet to the FIFO. Usedw starts from 2 and the FIFO goes full, but the status signals don't chance. 

 

At closer inspection with RTL Viewer, the empty and full signals seem to be static values generated in the fifo_state (a_fefifo) module. I have attached a picture of that as well. 

 

Is this a bug in the FIFO implementation, or is there something wrong with my parameters or some change in the recent version I have not noticed? I am now compiling the project with the FIFOs implemented on RAM blocks for testing. 

 

I am using the following parameters to instantiate the FIFO (ram output register and over/underflow checks were previously on): 

... parameter BYTES = 32, parameter WIDTH = 8, parameter CHANNELS = 4, parameter ERROR_WIDTH = 2, parameter DEVICE_FAMILY = "Arria 10", parameter BUFFER_DEPTH = 4 ... scfifo# ( .intended_device_family (DEVICE_FAMILY), .lpm_width (BYTES*WIDTH + $clog2(BYTES) + 2 + $clog2(CHANNELS) + ERROR_WIDTH), .lpm_widthu ($clog2(BUFFER_DEPTH)), .lpm_numwords (BUFFER_DEPTH), .lpm_type ("scfifo"), .enable_ecc ("FALSE"), .add_ram_output_register ("OFF"), .lpm_showahead ("ON"), .overflow_checking ("OFF"), .underflow_checking ("OFF"), .use_eab ("OFF") ) fifo_buf ( .clock (clk), .wrreq (in.valid & ~fifo_full), .data ({in.data, in.empty, in.sop, in.eop, in.channel, in.error}), .usedw (fifo_usedw), .full (fifo_full), .empty (fifo_empty), .rdreq (out.ready & out.valid), .q ({out.data, out.empty, out.sop, out.eop, out.channel, out.error}), .aclr (arsthttps://alteraforum.com/forum/attachment.php?attachmentid=15725&stc=1https://alteraforum.com/forum/attachment.php?attachmentid=15726&stc=1), .almost_empty (), .almost_full (), .eccstatus (), .sclr () );  

 

Edit: Switching to RAM-implemented FIFO worked, but still curious to find out why this happened.
0 Kudos
0 Replies
Reply