SCFIFO wrreq and rdreq synchronisation

[Altera_Forum]

Hi folks, 

just a quick question (hopefully),  In the SCFIFO megafunction I want to know if the wrreq and rdreq signals are synchronised to the clock input. That is to say, if I clock the FIFO with my system synchronous clock, but make a write request to the fifo from an asynchronous source, does the megafunction sync it to my system clock for me, or am i expected to put in a two stage sync myself?  likewise for the rdreq signal?  The user guide seems to suggest that it is done for me, but I wasnt entirely sure!  many thanks for any advice.  deBoogle

[Altera_Forum]

You will need to do the resynchronisation yourself. 

But why would you do that, when you can use the DCFIFO megafunction...

[Altera_Forum]

Hi Tricky, 

I did consider the dual clock FIFO, but was sort of hoping I could get away without having to bring the async clock from an external source into the FPGA (purely for electrical reasons). And my thinking was that I could resync the wwreq and rdreq signals to my system clock running at twice the async clock, and in the process generate myself a rise edge/ fall edge pulse. Then as long as I spec a suitable hold time for data on the bus I should be OK.  How ever in hindsight, it may be the better option to go for the DCFIFO. Is there anything inherently wrong with my initial idea? Is it workable?  Thanks for your help  deBoogle

[Altera_Forum]

Your idea could work, as long as you only use either the rising or falling edge pulses as the read/write request.  

But Personally I would want the system clock to be > 2x async clock for this. Anything less and you're going to loose the bandwidth.   And anyhow, why take the risk of a difficult to constrain clock domain crossing with all the possible bugs, when you could use an IP designed for this very purpose (the DCFIFO).

[Altera_Forum]

Thanks Tricky. 

 You make a fair point, and it is probably worth my while bringing the async clock source into the FPGA.  Many thanks once again. deBoogle