Hallo
I am designing a multi-rate filter block. My input signal is 44.1 kHz and output signal is 11.2 MHz. I have designed an I2S slave receiver to get the input and then pass it through my two upsampling filters 32 and 8 times. I use a rate transition block in between the I2S and the filter blocks to bring the input to the filter back to 44.1 kHz as the I2S bit clock is 64 times the input signal, the output signal from I2S block is also 64 times. I am doing my model in Simulink and generating the HDL code from there and then use Quatras to download the design to the FPGA.
But when i look at the output signal, there seems to be a problem with the timing as i loose almost half of the data at the output. I am using the basic SDC file from Quatras with out any PLL. As my input clock to the FPGA is 22.56 MHz and thats the same speed i run my design with. The following is my SDC file. Could any one please suggest me if the error is because of my SDC file and i need to do some changes on the SDC file
# Constrain clock port clk with a 44.289-ns requirement
create_clock -period 44.289 [get_ports clk]
# Automatically apply a generate clock on the output of phase-locked loops (PLLs) # This command can be safely left in the SDC even if no PLLs exist in the design
derive_pll_clocks
derive_clock_uncertainty
# Constrain the input I/O path
set_input_delay -clock clk -max 3 [all_inputs]
set_input_delay -clock clk -min 2 [all_inputs]
# Constrain the output I/O path
set_output_delay -clock clk -max 3 [all_outputs]
set_output_delay -clock clk -min 2 [all_outputs]
