Hi All,
How can I create the timing constraints (set_input/output_delay) for all ports (excepting clocks and reset ports)? Let's say the design has the following clocks: clk0, clk1, clk2 and following resets: rstn0, rstn1, rstn2 and hundreds of other ports. How can I write a script, which set input delays of 0ns for all input ports (excepting clk0, clk1, clk2, rstn0, rstn1, rstn2) and output delays of 0ns for all output ports? Thank you!連結已複製
If you read_sdc first, you can only do a syntax check. If you do it in the other order, you can apply the constraints as they're read in, which in some cases is necessary.
If the only thing you ever ran was read_sdc, then update could be implied, but it's possible to do read_sdc and then something like "read_sdc uncertainty_constraints.sdc", i.e. read a file that is not automatically pulled in by the project. Seldom done, but since it's a script it's better to break out the options. In the GUI, if you click on any of the reports then all three are done automatically in the correct order.What actually does the command create_timing_netlist? Does it create a seperate Netlist with timing arcs?
In the read_sdc command, there is a switch '-hdl': read_sdc -hdl. as far as I understand it gives an option to read SDC commands from HDL. So, how is it possible to embed SDC commands into HDL? Could you provide an example please?Yes, it has timing arcs and basically the model. Note that it also sets the model used, e.g. Slow 100 corner, or something like that.
It is not recommended to embed constraints. There was a way to do it but it's really ugly and it has no scope(so it doesn't just apply to the file it's in, but is read like a generic constraint). Altera used to use this internally, but now tries to create an explicit .sdc for all IP and include it with a .qip file.I've been answering piecemeal some of the questions, but stepping back:
1) In real life, you'd never want a script that adds 0 delay to everything, as there is no way those are the real constraints. I assume you just want this as a placeholder or something for a test design, like when compiling a submodule(although in that case I recommend not constraining the IO, since they're not really top-level ports) 2) set_input/output_delay constraints are difficult for a generic constraint because they require a -clock option to describe the register outside of the FPGA that launches or latches the data. If you have multiple clocks, then you need to know which IO are on which domain and that would not be easy to script. (I can think of some ugly ways, like constrain them to every clock and then cut the ones that aren't real, but again, ugly) 3) For simple IO constraints, set_max_delay and set_min_delay tend to work just fine and don't matter care what the clock is. So you could have an .sdc that does: set_max_delay -to [all_outputs] 10.0 set_min_delay -to [all_output] 0.0 (I forget if it's -to or -from, to be honest. This is similar to asking for a Tco of 10ns and min Tco of 0ns. On the input side, you may not want clocks and resets to be constrained, so do: set clocks_and_resets [get_ports clk1 clk2 clk3 reset1] ;# Manually enter your clock names here set data_inputs [remove_from_collection [all_inputs] $clocks_and_resets] set_max_delay -from [$data_inputs] 10.0 set_min_delay -from [$data_inputs] 0.0 (In this case 0 may be hard, as there will be clock skew to the latching register in the FPGA, and so data needs to be added to get the delay above that. Personally I would suggest a negative number)To Ryan's point about scripting with set_input_delay or set_output_delay, that's why we recommended setting up a virtual clock. As long as you have a virtual clock constraint for whatever is driving the upstream or downstream device, you can create set_input or set_output_delay constraints and make them generic.
