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15559 Discussions

SISO testbench and waveform HELP

Altera_Forum
Honored Contributor II
2,411 Views

Hello, i am new to VHDL and i want some directions. 

I want to make a Serial in serial out 4 bit shift register, but my waveforms in output have some red marks as you can see below. 

https://alteraforum.com/forum/attachment.php?attachmentid=15351&stc=1  

 

I am posting my testbench too. I d be grateful if you help me with that, because i am doing a project at the university. 

ENTITY Siso_Tb IS 

END Siso_Tb; 

 

ARCHITECTURE behavior OF Siso_Tb IS  

 

-- Component Declaration for the Unit Under Test (UUT) 

 

COMPONENT Siso 

PORT( 

Sin : IN std_logic; 

clk : IN std_logic; 

reset : IN std_logic; 

enable : IN STD_LOGIC; 

Sout : OUT std_logic); 

END COMPONENT; 

 

 

 

--Inputs 

signal Sin : std_logic := '0' ; 

signal clk : std_logic := '0'; 

signal reset : std_logic := '0'; 

signal enable : std_logic := '0'; 

 

 

--Outputs 

signal Sout : std_logic := '0'; 

 

 

-- Clock period definitions 

constant clk_period : time := 10 ns; 

 

BEGIN 

 

-- Instantiate the Unit Under Test (UUT) 

uut: Siso PORT MAP ( 

Sin => Sin, 

clk => clk, 

reset => reset, 

enable => enable, 

Sout => Sout); 

 

 

-- Clock process definitions 

clk_process :process 

begin 

clk <= '0'; 

wait for clk_period/2; 

clk <= '1'; 

wait for clk_period/2; 

end process; 

 

clk_enable :process 

begin 

enable <= '0'; 

wait for clk_period/2; 

enable <= '1'; 

wait for clk_period/2; 

end process; 

 

 

 

-- Stimulus process 

stim_proc: process 

begin  

 

reset <= '1';  

wait for clk_period/2; 

reset <= '0';  

wait for clk_period/2; 

 

Sin <= '1'; 

Sout <= '0'; 

wait for clk_period; 

 

Sin <= '0'; 

Sout <='0'; 

wait for clk_period; 

 

Sin <= '0'; 

Sout <='1'; 

wait for clk_period; 

 

Sin <= '1'; 

Sout <='0'; 

wait for clk_period; 

 

Sin <= '0'; 

Sout <='0'; 

wait for clk_period; 

 

Sin <= '0'; 

Sout <='1'; 

wait for clk_period; 

end process; 

 

 

END;
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3 Replies
Altera_Forum
Honored Contributor II
1,234 Views

You're driving Sout in the testbench, and the UUT is also driving Sout. Only the UUT should be driving SOut.

Altera_Forum
Honored Contributor II
1,234 Views

 

--- Quote Start ---  

You're driving Sout in the testbench, and the UUT is also driving Sout. Only the UUT should be driving SOut. 

--- Quote End ---  

 

 

You mean i should not change the values of Sout in the process? When i do it Sout is always 0.
Altera_Forum
Honored Contributor II
1,234 Views

SOUT is an output from the UUT. Therefore the UUT sets the value of Sout. If it is always 0, then there is a problem with the UUT, or th way you're driving the UUT. 

The X values occur because you are driving '1' against the value of '0' from the UUT. 

 

I also notice you are generating enable like a clock. and therefore likely never actually enabling the UUT. It needs to be set for full clock cycles, not half cycles.
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