SOC priority rule question

[Altera_Forum]

Hello, 

 I have a question regarding SOC rules and their priorities.  I use on my design a double clocked memory block. The logic runs at clock1x = 100 Mhz and the memory block uses clock2x = 200 Mhz. Both clocks are syncron. The 1 write port to the memory block accept writes on the fast clock, e.g. two writes per cycle from the slow clock domain.  Let for this example call them wp1_data_d, and wp2_data_d they are both clocked on clkc1x. The registered memory latch runs on the fast clock2x.    The logic creating the wp1_data_d is short and has no problem to reach the 200Mhz clock The logic creating the wp2_data_d is more and can only reach the 100 MHz clock.  Per default Timequest assumes that both have 1 cycle time to the memory_register. I would like to set multicycle 2 for the wp2_data_d.  What is the correct way to set this?  Would this term be correct: set_multicycle -setup -end -through [get_pins {mydesign|wp2_data_d*}] -to [get_clocks {pll|clock2x}] 2 set_multicycle -hold -end -through [get_pins {mydesign|wp2_data_d*}] -to [get_clocks {pll|clock2x}] 1  What happens if I would say it the other way around and give ALL signal form clkc1x to clck2x 2 cycle time and would like to only give the signal which only have 1 cycle an exception rule? Could I write the SDC file also that per default I give this rule: set_multicycle -setup -end -from [get_clocks {pll|clock1x] -to [get_clocks {pll|clock2x}] 2 set_multicycle -setup -end -through [get_pins {mydesign|wp1_data_d*}] -to [get_clocks {pll|clock2x}] 1 Here both rules overlap, Would this work?Many thanks in in advance

[Altera_Forum]

An SDC command overwrites previous command if referring to same path. Default multicycle of 1/0 is assumed unless overwritten. Similarly you can set a group of paths to any value then exclude some by overwriting in a next statement. 

 As to multicycle path being correct or not. That is difficult to judge from posts. The best thing is to see waveforms or even add test delay using after statement in a working testbench if practical or use timing simulation which would be too slow.

[Altera_Forum]

I think the second way to constraint fulfills your requirement as well because the command "set_multicycle -setup -end -through [get_pins {mydesign|wp1_data_d*}] -to [get_clocks {pll|clock2x}] 1" only overlaps the specified path. However, it is better to check the in TimeQuest whether it is being ignored and the timing relationship on those paths.