SOF file checksum

[Altera_Forum]

Hi all, 

 I want to inject Single Event Upsets (SEU) into cyclone II FPGA ... i want to make some bit flips in SOF file and download the corrupted bit file to Cyclone II FPGA ... but the programmer does not allow this and responds with a message "This device is not supported" .... I know that this is because of the checksum violation... Can anybody suggest answers to the following 1- where in the SOF file the 32 bit checksum is located?  2- how to recompute the checksum ?  3- what is the value of 32 bit generator polynomial for CRC?  Or any other alternative method for injecting faults in altera FPGAs  Kind Regards

[Altera_Forum]

Hello  

 You can find the information you are requiring in the CycloneIII Handbook  Chapter 11. seu mitigation in the cyclone iii device family  1 - Quartus adds a 32bit pre-calculated CRC value at the end of sof file. This file is located to your project directory. Also, a 16bit CRC is added in each CRAM frame.  2 - You are not able to recompute the checksum.This is automatic calculated by the Hard logic circuit in the fpga.  3 - I think that you can read the 32bit CRC register via your jtag interface  Thank you  Dimitrios Agiakatsikas

[Altera_Forum]

--- Quote Start ---  Hello   You can find the information you are requiring in the CycloneIII Handbook  Chapter 11. seu mitigation in the cyclone iii device family  1 - Quartus adds a 32bit pre-calculated CRC value at the end of sof file. This file is located to your project directory. Also, a 16bit CRC is added in each CRAM frame.  2 - You are not able to recompute the checksum.This is automatic calculated by the Hard logic circuit in the fpga.  3 - I think that you can read the 32bit CRC register via your jtag interface  Thank you  Dimitrios Agiakatsikas  --- Quote End ---      how about rbf ? how can i figure out what is the data mean in the rbf file ?