SOLUTIONS??Laboratory Exercise 5 Timers and Real-time Clock

[Altera_Forum]

hi wanted to know the solution of this exercise: 

 Listing 1: A VHDL description of an n-bit counter. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; entity counter is generic ( n : natural := 4; ); port ( clock : in std_logic; reset_n : in std_logic; q : out std_logic_vector(n-1 downto 0) ); end entity; architecture rtl of counter is signal value : std_logic_vector(n-1 downto 0); begin process(clock, reset_n) begin if (reset_n = ’0’) then value <= (others => ’0’); elsif ((clock’event) and (clock = ’1’)) then value <= value + 1; end if; end process; q <= value; end rtl;   The parameter n speci es the number of bits in the counter. A particular value of this parameter is de ned by using a generic map statement. For example, an 8-bit counter can be speci ed as:   e i g h t b i t : count e r g e n e r i c map( n => 8 ) por t map e i g h t b i t ( c lock , r e s e t n , q) ;    By using parameters we can instantiate counters of di erent sizes in a logic circuit, without having to create a new module for each counter. Part I Create a modulo-k counter by modifying the design of an 8-bit counter to contain an additional parameter. The counter should count from 0 to k &#1048576; 1. When the counter reaches the value k &#1048576; 1 the value that follows should be 0. Your circuit should use pushbutton KEY0 as an asynchronous reset, KEY1 as a manual clock input. The contents of the counter should be displayed on red LEDs. Compile your design with Quartus II software, download your design onto a DE1 board, and test its operation. Perform the following steps: 1. create a new quartus ii project which will be used to implement the desired circuit on the de1 board. 2. write a vhdl le that speci es the desired circuit. 3. include the vhdl le in your project and compile the circuit. 4. assign the pins on the fpga to connect to the lights and pushbutton switches, by importing the pin-assignment le de1 pin assignments.qsf. 5. compile the circuit and download it into the fpga chip. 6. verify that your circuit works correctly by observing the display.

[Altera_Forum]

study more

[Altera_Forum]

You are the student, this is your assignment. We are not here to make your homework.

[Altera_Forum]

--- Quote Start ---  You are the student, this is your assignment. We are not here to make your homework.  --- Quote End ---   explain to me a bit like starting with the code, Please

[Altera_Forum]

I would recommend you to get a VHDL textbook or do some tutorials as a start. Altera for example has a "VHDL Basic" course for free on their website, see http://www.altera.com/education/training/courses/ohdl1110 (http://www.altera.com/education/training/courses/ohdl1110), which is part of the "FPGA Designer Curriculum" http://www.altera.com/education/training/curriculum/fpga/trn-fpga.html (http://www.altera.com/education/training/curriculum/fpga/trn-fpga.html) .

[Altera_Forum]

I've been studying the code for this exercise, but I erorr 

code; library ieee;   use ieee.std_logic_1164.all;  use ieee.std_logic_arith.all;  use ieee.std_logic_unsigned.all;   entity counter is  generic (  n : integer := 4;  k : integer := 8 );    port   (  clock : in STD_LOGIC;  reset_n : in STD_LOGIC;  Q : out STD_LOGIC_VECTOR(n-1 downto 0);  SW: in std_logic_vector(7 downto 0);  KEY : in std_logic_vector(1 downto 0);  LEDR : out std_logic_vector(7 downto 0)  );     end counter;   architecture rtl of counter is  signal Q_int: std_logic_vector(n-1 downto 0); begin PROCESS(clock, reset_n) begin  if (reset_n = '0') then    Q_int<= (others => '0'); elsif ((clock'event) and (clock = '1')) then  if Q_int>= k-1 then    Q_int<= (others => '0');    else   Q_int <= Q_int + 1;    end if;  end if;  end process;  Q <= Q_int; end rtl;    architecture Behavioral of counter is  component counter  generic  (  n : integer := 4;  k : integer := 8  );  end component; begin  eight_bit: counter   generic map ( n => 8, k => 4)  port map eight_bit( clock, reset_n, Q, KEY(1), KEY(0), LEDR );  end Behavioral;

[Altera_Forum]

What kind of error? 

I don't know what VHDL course you are following, but it's not recommended to use ieee.std_logic_unsigned.all. It's non standard and it won't let you use signed arithmetic in the same code. Use ieee.numeric_std.all instead.