SOPC Builder Error: Can't generate 2X sampling clock signal...

[Altera_Forum]

I'm trying to modify the DE2_70_Camera demonstration for the DE2_70 board. However, when I open the SOPC Builder file, there's an error that says "Error: cpu: Can't generate 2X sampling clock signal due to limited number of PLLs in this device family. Please connect 2X sampling clock manually" that prevents me from generating the design. I'm not sure what it means, or how to "connect the 2X sampling clock manually". Any pointers?

[Altera_Forum]

Did you ever get a resolution to this issue, I have found the same problem, I'm trying to work with the DE2-70 camera design and see the same 2x sampling clock error when I open the SOPC design

[Altera_Forum]

Yeah, I finally got it. In SOPC Builder, double click on the CPU to bring up the options window for it. Click on the "JTAG Debug Module" tab and then down in the bottom left corner, under "Advanced Debug Settings" there's a checkbox for "Automatically generate internal 2X clock signal". After unchecking that box, the error will go away and you can generate your design. Unchecking the box doesn't seem to have any negative effect as I've now been able to generate the design, synthesize it in Quartus and deploy it on the board including using the NIOS II IDE to reprogram the processor inside and use the debugger with it. Hope this helps.