SOPC Builder .qip file is missing all the HDL source files

Altera_Forum · ‎07-07-2011

Hi, I'm trying to use a SOPC Builder system for two projects located in two different directories, so I need to explicitly tell Quartus the paths to the source files so that it can find them. I'm trying to use the auto-generated .qip file for the SOPC Builder system, but for some reason it's almost completely empty! It doesn't list any of the .vhd or .v files for my system, only a few miscellaneous files:

# clk
#  tri_state_bridge_0
#  cfi_flash_0
#  timer0
#  jtag_uart_0
#  cpu_0
set_global_assignment -name SDC_FILE 
set_global_assignment -name SOURCE_FILE 
#  sysid
#  watchdog_timer
#  altmemddr_0
#  null
set_global_assignment -name SDC_FILE 
set_global_assignment -name SOPC_BUILDER_SIGNATURE_ID ...

I tried using Qsys instead but it can't generate my system at all. :/

Does anyone know how to make SOPC Builder generate a correct .qip file?

Altera_Forum · ‎07-07-2011

I remember the fact the qip file doesn't list the source files is a known issue/feature and it was discussed in the forum some time ago for Quartus version 9.0. This is also the reason you had a lot of warnings (sort of "hdl file not included in project") during project compilation.

I think your problem is related to this: you need to have the qip file and the sopc builder auto generated hdl files in the same directory of your project, so that Quartus can find them anyway.

Unfortunately I don't know if there is a workaround, apart manually copying the required sopc files in both projects.

Altera_Forum · ‎07-27-2011

For anyone else experiencing this problem, I ended up working around it by writing a TCL script that generates the appropriate assignments from the PTF when the QIP is loaded

I created a util_qip_from_ptf.tcl file containing:

proc util_qip_from_ptf {filepath} {
  set fp 
  lappend map __PROJECT_DIRECTORY__ 
  while { >= 0} {
    if {*Synthesis_HDL_Files = "(.*)";$} $line {\1} line]} {
      foreach hdl_file  {
        set hdl_file ]
        if { ".vhd"]} {
          set setting_name VHDL_FILE
        } elseif { ".v"]} {
          set setting_name VERILOG_FILE
        } else {
          puts "Ignoring unknown HDL file type: $hdl_file"
          continue
        }
        set_global_assignment -name $setting_name $hdl_file
      }
    }
  }
}

and I made my own fake .qip file containing:

set_global_assignment -name IP_TOOL_NAME "Fake QIP File"
set_global_assignment -name IP_TOOL_VERSION "1.0"
source 
util_qip_from_ptf

Altera_Forum · ‎07-28-2011

thanks for sharing!