SOPC Builder "Validation Error"

Altera_Forum · ‎07-23-2008

I'm new to altera software and am attempting to use SOPC Builder to build a Nios II system. I'm using Quartus II v8.0 service pack 1. But when I click generate after adding the components in SOPC builder, I get this error:

"Error: Generation skipped because system has validation errors."

Any ideas on what is wrong/what I should do? I can provide more details if needed

Altera_Forum · ‎07-24-2008

Can you see any errors on bottom window (just above 'Next', 'Help', etc. buttons) of SOPC Builder when you have selected 'System Content' tab. If there is any error try to fix it first before generating system. It is better if you can provide more details or screen shots!

All the best!

Altera_Forum · ‎10-02-2008

I too have the same problem. But then there seems to be no other errors when I am try generating the design. I am trying to run the example which is provided by Altera, Tutorial on SOPC builder. The one to simulate the lights....

I had tried this one earlier on a different system putting the On-Chip memory parameter to Auto... but this time I tried putting it on M4K memory block.

I am not sure what might be the error... any info onto this...

Altera_Forum · ‎10-02-2008

Try this: Go to the Nios II cpu config and make sure that you set the Reset and Exception vectors. That fixed the problem for me.

Altera_Forum · ‎12-06-2008

you must edit "memory on chip" (if you use it) in the cpu , then you can normal generation

Altera_Forum · ‎08-14-2009

Hello there,

New to the forums, and yeah the same problem brought me here. Setting the reset and exception vectors fixed it for me too. Don't quite understand why, if anyone would explain I'd be grateful. Im sure there may be a couple out there who'd like to know the reason why this fixes the issue.

Secondly where can I see the error log in SOPC builder like we can see in Quartus (mother program?)

Last post suggested 'editing the on-chip memory' without giving too much detail about what to edit in it? Could someone elaborate? Im sorry if I sound naive but Im a noob w.r.t. NIOS:D

Keen to hear from you people.:)

Altera_Forum · ‎08-14-2009

If there are any problems in your SoPC system, they usually show up at the bottom of the screen in the little information window. You must resolve these errors before generating the system.

Not setting the reset and exception vectors for the processor is an error and you cannot generate the system until you've resolved it.

SoPC builder prints out a log file "<name_of_your_system>_log.txt" during generation.

With regards to the post about editing the memory, I think maybe what he was trying to reiterate the fact that you have to set the reset and exception vectors. Sounds like in his simple case, he was using onchip memory for those vectors. What you set the reset and exception vectors to is dependent on your system, there is no "one size fits all" value.

Jake

Altera_Forum · ‎08-15-2009

Hi there jake,

thanks for the prompt reply. Still got some stuff to talk and here it is:

You said -
--- Quote Start ---
If there are any problems in your SoPC system, they usually show up at the bottom of the screen in the little information window. You must resolve these errors before generating the system.
--- Quote End ---
. In this case, it didn't explicitly say anything about the reset and exception vectors, rather just talked about the 'validation errors' so in this case a noob would find it hard to figure out the source.
you said -
--- Quote Start ---
Not setting the reset and exception vectors for the processor is an error and you cannot generate the system until you've resolved it.
--- Quote End ---
. This is obvious in keeping with the principles of computer design now isn't it? assuming the soft core has built in routines to service requests for reset and during an exception. But a regular core like x86 or ARM seem to have fixed routines to serve exception faults like a divide-by-zero error etc whereas the soft core here seems to have a generic address to serve resets and exceptions. As you said, these routines could be stored on the on-chip memory, but didn't specify how or where.
Im following the SOPC VHDL tutorial downloaded from the altera FTP site. I have now been able to get a VHDL model of the system which I have instantiated in my top level design file but im running into compile time errors. Heres the code:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY lights IS
  PORT (
    SW       : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
    KEY      : IN  STD_LOGIC_VECTOR(0 DOWNTO 0);
    CLOCK_50 : IN  STD_LOGIC;
    LEDG     : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
    ); 
END lights;
ARCHITECTURE Structure OF lights IS
  COMPONENT nios_system
    PORT (
      clk                     : IN  STD_LOGIC;
      reset_n                 : IN  STD_LOGIC;
      out_port_from_the_LEDs  : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
      in_port_to_the_Switches : IN  STD_LOGIC_VECTOR (7 DOWNTO 0)
      ); 
  END COMPONENT;
  BEGIN 
  -- Instantiate the Nios II system entity generated by the SOPC Builder 
    
  nios_system_inst : nios_system
    port map(    
      out_port_from_the_LEDs => LEDG,
      clk => CLOCK_50,
      in_port_to_the_switches => SW,
      reset_n => KEY(0)
      );
END Structure;

I get an error that says "Error: Port "clk" does not exist in macrofunction "nios_system_inst" ". Why is the component instantiation referred to as a 'macrofunction' ? Could you provide me with some pointers?

Hoping to hear from you and thank you for your help.

Regards,

Aijaz Baig.