- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
I have to modules which have ports that have to be connected together. This time i have exported (conduit end) the ports to the top-level an then i connect them externally in my vhdl-code. Is it possible to connect ports of SOPC-Components togeher internally (in the SOPC-System)? Thanks, PaddyLink Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
You can't connect conduits between components in SOPC builder. You can in QSys though.
If you can manage to make your conduit interface look like a standard Avalon interface (such as stream sources/sinks) then you could connect them together in SOPC builder.- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Thanks for your quick reply.
Thats a "good" answer for me, cause i want to migrate to qsys soon. Thanks again Paddy- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
If possible I would try to use standard interfaces over conduits. Qsys will treat everything in the conduit as just a blob of signals/buses and will not be able to do much checking for you that they are wired correctly. Typically I use ST without flow control instead of conduits since things like the clock domains of each port will be validated for you by Qsys which isn't possible with conduits.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
So you mean that i should use avalon ST-Signals for my internal connections? Which signals can i use (channel, data, error)? Are they directly connected together if i connect them in SOPC?
Thanks, Paddy- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I typically just use the 'data' signal in cases like these. The data signal is the only mandatory signal in the ST spec and all you have to do is declare what clock domain it's on since ST interfaces are synchronized. In the case of just sending a signal down the data line you are not forced to synchronize the signal internally, it's just that you wouldn't be able to insert standard ST adapters into the data path if you are using ST in a combinational way.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Ok, i think now i understood what you mean. It seems to be a smart way to get my internal connections. I'll try this out.
Thanks for your help, Paddy- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I also recommend building gasket blocks that take all the signals and jam it into a wide ST data signal and visa versa. This should make it easier to add/remove/modify signals inside the big bundle of wires on each end. I also typically make the ST interface 256 bits wide (and pad unused signals to 0) so that I can add more signals without having to make the ST interface wider by hacking up the .tcl file.

- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page