SOPC problem using Avalon-MM tristate bridge and memory

[Altera_Forum]

I'd like have some memory in my design that is on-chip (dual port) but outside the SOPC so that I can connect to the second port. This looks possible when I add an Avalon-MM tristate bridge and an IDT71V416. Why can't I connect internal RAM in place of the IDT71V416 in SOPC builder?

[Altera_Forum]

this would be easy in Qsys, you could internally connect 1 of the RAM ports inside of Qsys and export the other so it is accessible outside of Qsys 

 you don't want a tri-state bridge, as you've found that's meant for external interfaces. you can create a custom component using the Avalon MM Master template. i don't think any other changes need to be made. connect your internal SOPC Builder MM Master to one port and your dummy custom component to the other. when you generate you should have the Avalon MM Master ports on your system  alternatively you can pull whatever is outside of SOPC Builder in as a custom component

[Altera_Forum]

I'm confused by the suggestion to use the MM master template as my current approach is to design an HDL component with an Avalon MM slave port and a bunch of external ports. It's looking a bit ugly as there are a lot of external ports. 

 The logic outside SOPC is big and nearly all done in schematic, so I don't fancy writing an HDL wrapper for it.

[Altera_Forum]

i think i had your situation backwards, i thought you wanted to connect a RAM in SOPC Builder to the outside world 

 to connect SOPC Builder to RAM on the outside, your approach of using the MM Slave template is correct

[Altera_Forum]

I've defined a custom synchronous SRAM and that seems to work. It's a bit clunky because the data bus comes out of the SOPC block as a bidirectional bus, but it seems to work.

[Altera_Forum]

--- Quote Start ---  I'd like have some memory in my design that is on-chip (dual port) but outside the SOPC so that I can connect to the second port. This looks possible when I add an Avalon-MM tristate bridge and an IDT71V416. Why can't I connect internal RAM in place of the IDT71V416 in SOPC builder?  --- Quote End ---     when SRAM added in the sopc builder in niosii processor configuration i am getting an error saying that "Error: sram_0: sram_0.s1 must be connected to an Avalon-MM Tristate master" pls help

[Altera_Forum]

hi this is imran. 

can anyone help me for the following. if i use onchip memory then error flashes as follows. pls help regarding usage of onchip memory in accordance with hello world program in c.  if i need to use sram too then pls help for the same too.

[Altera_Forum]

hi this is imran  

can anyone help me for the following. if i run a project in c code in eclipse as nios II hardware then i get the following error message."Project does have an ELF file. Please make sure project has been built successfully"