SPI Slave Implementation

[Altera_Forum]

I am writing a code of SPI slave in FPGA. Is it necessary to sync my FPGA global clock and serial clock ? 

If so can someone tell me the pros & cons for the same ?

[Altera_Forum]

Yes. You would sample the serial clock using your global clock to detect when an edge occurs. Using the serial clock is not really a good idea.

[Altera_Forum]

--- Quote Start ---   Is it necessary to sync my FPGA global clock and serial clock?   --- Quote End ---   It depends on your hardware implementation. Here's two implementation options;  1. Use the SPI clock to serialize and deserialize bytes, and then use clock-domain crossing logic to send the bytes to the FPGA clock domain. This is how the SPI-to-Avalon bridge works.  2. Use the FPGA clock to "synchronize" (dual-DFF) the SPI clock, and then use an edge-detect (DFF delay and combinatorial logic) the pulses for rising-edge and falling-edge. Use an FSM in the FPGA clock domain to determine when to clock data in, or out.  I've used both techniques before. When using (1), you have to make sure your clock is clean, i.e., no ringing on the edges.  If your FPGA clock is much faster than your SPI clock, then I'd recommend using (2). If they are comparable, then (2) will not work, so you'd have to investigate using (1). If your FPGA has a PLL, then you could try both techniques.  Cheers, Dave

[Altera_Forum]

Thank You very much for your valuable reply...! 

I have some another question! Is it necessary to use CS(Chip Select) signal in SPI ? If I am using only one slave then can I connect this CS pin to ground permanently ?

[Altera_Forum]

--- Quote Start ---   I have some another question! Is it necessary to use CS(Chip Select) signal in SPI ? If I am using only one slave then can I connect this CS pin to ground permanently ?  --- Quote End ---   No, generally you should use a chip select.  Why? Because the SPI device uses chip-select to determine the start of a transaction.   For example, lets say your FPGA is the SPI master communicating with some SPI slave. What happens to the SPI clock during power on? As the FPGA turns on, if weak pull-ups are enabled, there will be a rising-edge, and then perhaps your SPI clock is reset low (i.e., the FPGA configured state drives SPI clock low). Does the SPI device consider this a single clock? Who knows?  You should read the data sheet for your device.  Use the SPI chip select and things will just work correctly.  Cheers, Dave