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Honored Contributor I

SPI core as Master mode?

Hi. Still getting the ropes here. I'm including SPI peripherals to my design for Max10 FPGA. Is it possible instantiate an SPI core in Platform Designer as master?, using Max10 FPGA?, Quartus Prime 17.1 Lite?, Platform Designer?  



I seem to be coming up empty handed, but may not be using the right search terms. To know i'm on the right track or not, i'd just like to be sure that what i'm looking for exists. I see some reference of problems as mater, but it doesn't appear to be listed in the SPI core documentation for some reason. Slave/Master is ambiguous when either side can be either function. Perhaps I should be looking at the 'SPI Slave to Avalon Master Bridge'? Thanks so much for your help.
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Honored Contributor I

So to clarify, I see many mentions of SPI Master mode in the docs and vids, but have yet to land on what register to set, or which core variant of those available should be chosen, in order to instantiate a SPI master in Max10 to address and read/write SPI peripherals. It is ambiguous when just getting the ropes. 


The Avalon SPI core doc. PDF references both modes, but doesn't show how to set master more, unless my eyes are just not seeing it. Also there is no dialog entry to set 'master' or 'slave' when adding SPI core to Platform Designer. 


Yet From Altera 'Embedded Peripherals IP User Guide' it suggests I can set the mode myself: 

5.2.4. Master and Slave Modes 

At system generation time, the designer configures the SPI core in either master 

mode or slave mode. The mode cannot be switched at runtime. 


But how? Is there a document I haven't found yet? Thanks in advance.

In Quartus 17.0 Lite edition, you can find the SPI core which can be set to master/slave under the "SPI (3 wire serial)" core in the Qsys IP Catalog. I think that's what you're referring to.