I'm trying to implement following verilog peace of code in vhdl
reg [11:-2]center; it's clear center is an 14 bit register. but in vhdl signal center : std_logic_vector(11 downto -2) gives me an error. what should i do ? i know that std_logic_vector type cannot use to index negative values. please help me. :(链接已复制
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std_logic_vector(13 downto 0) and offset everything by 2. Not really any other way around it for std_logic_vector. Why has the value got -ve indices? is it a fixed point value. The fixed point types allow negative ranges as they provide bit that represent numbers that are 2^N (ie. -ve indeces are to the RHS of a decimal point: signal centre : ufixed(11 downto -2);i'm trying to design a game using vhdl. an original source for this game was found in verilog. in that they used this negative indexing inside reg. i tried to chnage the reg indexing as reg[13:0] and game did'nt worked. original verilog code as follows
// Used for drawing, moving and updating of walls module walls( input clk, input update, input [5:0]data, output wire hold, output wire [5:0]data_addr, input [2:0]quadrant_collision, input [9:0]radius_collision, input [2:0]quadrant, input [9:0]radius, input reset, input [1:0]difficulty, output reg [2:0]quadrant_out, output reg visible, output reg island, output reg visible_collision ); reg [5:0]walls[0:127]; reg [11:-2]center; reg [6:0]write_ptr; wire [11:0]offset = center[11:0] + radius; wire [11:0]offset_collision = center[11:0] + radius_collision; integer i; always @(posedge clk) begin if(reset) begin center <= 14'd6144; end else if(update) begin case(difficulty) 2'd0: center <= center + 14'd6; 2'd1: center <= center + 14'd9; 2'd2: center <= center + 14'd12; 2'd3: center <= center + 14'd15; endcase end end always @(posedge clk) begin quadrant_out <= quadrant; if(radius < 10'd28) begin visible <= 1'b0; visible_collision <= 1'b0; island <= 1'b1; end else if(radius < 10'd32) begin visible <= 1'b1; visible_collision <= 1'b0; island <= 1'b0; end else begin visible <= walls[offset[11:5]][quadrant+:1]; visible_collision <= walls[offset_collision[11:5]][quadrant_collision+:1]; island <= 1'b0; end end assign data_addr = write_ptr[5:0]; assign hold = write_ptr[5:0]!=6'd0 || (write_ptr==7'b0000000 && center[11]) || (write_ptr==7'b1000000 && !center[11]); always @(posedge clk) begin if(reset) begin write_ptr <= 7'b1000000; for (i=0; i<128; i=i+1) walls[i] <= 6'b000000; end else if(hold) begin walls[write_ptr] <= data; write_ptr <= write_ptr + 7'd1; end end endmodule--- Quote Start --- i'm trying to design a game using vhdl. an original source for this game was found in verilog. in that they used this negative indexing inside reg. i tried to chnage the reg indexing as reg[13:0] and game did'nt worked. original verilog code as follows --- Quote End --- Did you also offset all of the constants and additions and assignments that take place on center? everything needs to be left shifted by 2.
--- Quote Start --- thank you for the quick reply sir, what if i used following code instead using std_logic_vector signal center: integer range 0 to 16384 -- (13 downto 0) will it be the same ? --- Quote End --- Almost, I think you mean: signal center : integer range 0 to 16383; As this is 14 bits. 16384 requires 15 bits. But you still have the same problem as I outlined above - you need to offset everything else, not just the center signal.
