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I've inherited a bunch of mid-sized FPGA designs which were all done in schmatic form. Yeah yeah, I don't need to hear how deep in it I am.
I will convert this to VHDL, but in the meantime what I want to know is if there is a way to compare two schematic based designs in Quartus? Also, how can I choose a wire with its corresponding net name, and find out where it goes? Thanks for your help in advance!Link Copied
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i would try RTL Viewer to see if you can get an idea of where signals go
comparing designs will be difficult. if they are different revs of the same design, you may try to make sense of a diff output
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