Shift-Registers within LEs or RAM blocks ?

[Altera_Forum]

Hi, 

 My project has to serialize @250MHz an input flow of 16-sample parallel data packets that come out from M4K and M-RAM blocks @ 15.625MHz (250/16).  Instead of implementing a classical shift-register with LEs, is there a way to implement this shift register (loaded @15.625 and clocked @250MHz) with RAM blocks in order to avoid long interconnect delays between RAM blocks and LEs that would likely prevent me from running @250MHz (near 70% of an EP2S130 used for the time being…). In other words, a kind of “Byte Enable” feature but usable for the read operation (and not only an input data mask during the write operation as is it presently the case in Tri-Matrix RAM blocks).  Oliver

[Altera_Forum]

I'm not quite following what you're doing, but if you want to serialize the read, just making it a x1 data word on the read side. Your address width will grow by 4 bits, which you'll have to run with a counter, but that should do it.

[Altera_Forum]

Hello Rysc, 

 I mean my input data words are 32-Bit wide (16x2-Bit) and my output data words are 2-Bit wide (1x2-Bit). I was initialy planning to use the ALT_SYNCRAM megafunction in simple dual-port mode with same data width for a and b ports. Do you suggest to use different data width ? If so, what becomes the read address range ? For instance, if the write address range is 00 to FF would the read address range becomes FFF (16x FF) ?

[Altera_Forum]

Yep. By being configurable widths/depths, the memories already have built in muxes to choose how wide/deep you want it to be configured. You're just using that to your advantage since your read and write widths are different. You still have to control the addressing for these different scenarios, which is expected, but it should do what you want and not use extra serialize the data stream

[Altera_Forum]

Great !! 

I was fighting with the fitter to find a design structure that would minimize the data path length between the RAM output ports and my serializers (these node ICs reported by the timing analyzer lead to a Fmax 20% under my 250MHz requirement for the time being). Using the RAM "built-in" muxes should improve Fmax significantly ! Many thanks !  I find myself a little bit stupid not to think before to use different data port widths keeping in my mind that if you write N bits into a RAM address you have to read N bits as well, forgetting the flexibility provided by nowaday's FPGAs...  Thanks again (one point more for your reputation though it is already overflowed ;-) )  Oliver