Shift delay block (data valid) in simple PI controller using ALTERA FP libraries

[Altera_Forum]

Hello all, 

 I have a FPGA system running with 150MHz with some ADCs and doing some PWM. The system until now is handling 16bit signed integers.  I want to develop a simple floating point PI controller that runs at a sample rate of 100kHz, the simple block diagram of which is illustrated below:  https://www.alteraforum.com/forum/attachment.php?attachmentid=8708   Due to the fact that the floating point blocks (conversion, add, multiply, subtract blocks) introduce some calculation delay (150MHz clock cycles) in the system the whole process needs to be synchronized using a data valid 1-bit signal that gets propagated with the data through the calculation to denote the flow of the data as shown in the implementation below:  https://www.alteraforum.com/forum/attachment.php?attachmentid=8709   The same data valid signal is also used to trigger the control loop as this data valid signal is a 100kHz pulse with the width of a 150MHz clock of the FPGA. This valid data signal is also fed to a multiplexer block of the integrator loop so that only once per triggering cycle the output of the integrator is added as loopback and all the other FPGA 150MHz clock cycles a zero is fed (so that the integrator works only once inside the trigger cycle as it should do).  my question:   How do I introduce a "shift delay" to the data and valid signal so that I synchronize the system? The easy way is to add registers in series but sounds kind of dumm in case of 30 cycles delay for example.  Also:  Is there any theory or books behind synchronizing this kind of calculation operations?  Any answer to the aforementioned questions is welcome as I think that lots and lots of people will find this information useful!  Thanks in advance!

[Altera_Forum]

--- Quote Start ---   [/B]How do I introduce a "shift delay" to the data and valid signal so that I synchronize the system? The easy way is to add registers in series but sounds kind of dumm in case of 30 cycles delay for example.   --- Quote End ---    The method I usually use is to infer ALTSHIFT_TAPS in my code. See page 13-40 of this document: http://www.altera.com/literature/hb/qts/qts_qii51007.pdf

[Altera_Forum]

--- Quote Start ---  The method I usually use is to infer ALTSHIFT_TAPS in my code. See page 13-40 of this document: http://www.altera.com/literature/hb/qts/qts_qii51007.pdf  --- Quote End ---    Hey thanks!  I already found the shift register ready made code.  I would like to ask you though if there is any method or theory behind synchronizing more complex arithmetical calculations. For example if i need to make a resonant controller that has many feedback loops, how should I methodize the procedure?  Thanks in advance

[Altera_Forum]

Firstly I suggest to use fixed point arithmetic instead of floating point which reduces resource usage and number of pipeline stages. 

 Secondly I don't see the advantage of the high 150 MHz clock frequency with 100 kHz sample rate. A moderate clock like 40 or 50 MHz that allows to perform an elementary add or multiply operation in a single clock cycle seems more appropriate. I believe that you want a higher clock frequency for the PWM stage, but you can transfer the manipulated value to the fast clock domain before generating PWM signals.

[Altera_Forum]

--- Quote Start ---  Firstly I suggest to use fixed point arithmetic instead of floating point which reduces resource usage and number of pipeline stages.  Secondly I don't see the advantage of the high 150 MHz clock frequency with 100 kHz sample rate. A moderate clock like 40 or 50 MHz that allows to perform an elementary add or multiply operation in a single clock cycle seems more appropriate. I believe that you want a higher clock frequency for the PWM stage, but you can transfer the manipulated value to the fast clock domain before generating PWM signals.  --- Quote End ---    Thanks for the answer!!  Good comments but my focus is somewhere else:  First how do i plan the delay and synchronization of complicated designs with multiple feedbacks (do I do it by experience or is there any theory or methodology behind it?).  Second, since you mention it, fixed point will create another iteration loop in my design as I have to also think about word sizes and precision. But anyway is also some theory and methodology behind the fixed point design?  And third, can I escape all this (including delay design) by using DSP Builder?  Thanks in advance