Hi, As described below i have simulated with NIOSII, RAM & JTAG UART qsys system. Compiled and simulated the example Hello World C code program. From the simulation i see that it takes around 2 ms to complete the simulation. Before the NIOSII starts executing the main code to print, from NIOSII instruction bus to JTAG UART, there is lot of operations on NIOSII data bus to internal SRAM. Is it possible to shorten these operations from the boot code and replace them with memory initialisations with internal SRAM.
Are you using custom memory controllers models? This application note discusses the generic memory model and didn't mentioned the differences among all of the memories models.
No I am not using the custom memory models. I am using the generic memory model that is generated by default from the platform designer and simulating the same. Well, I am not really looking for any compiler options to shorten the code. But when I see in model sim simulations, during the boot code execution before jumping to main there is lot of operations performed by the NIOSII data bus on the internal onchip RAM. So my request is: Is there a possibility to remove some operations from the boot code and replace them with initialising the onchip RAM components (Note this is only for simulation purposes). I understand on the FPGA it will be the actual boot code that runs.
I understand that, but the Model Sim generates the same environment for the NIOS II to boot and run as normal live, this is not editable to simulate something else. It is simply a virtual device software that act as a live normal system.
The best way is to make all the system wait for 2ms or get an enable signal to control the other devices in order to get the NIOS II ready first and then start the execution with enabling everything at the same time.