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Sigasi has released its VHDL development environment as Eclipse plugin. You can read a white paper with the motivation on http://www.sigasi.com/content/why-hardware-designers-should-switch-eclipse
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Is it that much better than "emacs VHDL mode" ?
So far I could not found a better editor for VHDL. It simply rocks, I love it's "copy... paste as" capabilities.- Mark as New
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--- Quote Start --- Is it that much better than "emacs VHDL mode" ? So far I could not found a better editor for VHDL. It simply rocks, I love it's "copy... paste as" capabilities. --- Quote End --- It really is that much better :) It differs from other development tools in that it contains an ultra-fast vhdl parser and compiler that runs transparently in the background. At any given moment as you make modifications, the tool fully understands the design in terms of VHDL concepts. This technology makes it possible to support a wide range of powerful features: Intelligent navigation, instant error reporting, intelligent code completion, quickfixes, Refactoring, automatic updating of makefiles,... The intelligent auto-complete makes the "paste as obsolete" detour obsolete. With Sigasi HDT you can instantiate components with a single key stroke (Ctrl-Space) without having to copy anything first. Because it is an Eclipse plugin, you can combine it with other Eclipse plugins: version control support, bug tracker, ... This result in an extremely powerful and extensible development environment. I invite you to experience it yourself: http://www.sigasi.com/start Hendrik.
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Hi, I began to make "refactoring" in VHDL, you can see here : http://sourceforge.net/projects/npppythonscript/forums/forum/1199074/topic/5097194
It is a python script for notepad ++ (http://notepad-plus-plus.org/) with pythonscript plugin (http://npppythonscript.sourceforge.net/) It is incomplete, doesn't contain "Intelligent navigation, instant error reporting, intelligent code completion, quickfixes, automatic updating of makefiles,..." I have surfing on the web for tools that do "refactoring" in VHDL and Sigasi seems to be the best now (I didn't try). Maybe a future feature of Quartus (this is not as simply as you can think)- Mark as New
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Sigasi now runs the modelsim compiler when you save your files helping you to weed out more errors.
It will soon (I have access to the test-version) be able to import QII projects. Would be nice if they could generate a QII project , solving the chicken-or-egg problem when you have start a new project. Altera should definitely talk to these guys about licensing the technology to integrate it into Quartus?
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