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Valued Contributor III
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Signal output cannot be synthesized, bad synchronous description.

Hi , 

 

I have been using vhdl programming for my project and I am trying to make a counter to count clock signal(clk_plstr),the counter is reset with another pulse signal(plsrep in my code). 

I am successful in simulating the code but while I tried to implement in the design it gave me following error: 

 

"Signal output cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release." 

 

I am not sure what is this error about. Below is my part of code which I guess is giving this error: 

 

process(clk_plstr,plsrep) ----clk_plstr=10mhz;plsrep=2.5khz 

begin 

pls<=conv_std_logic_vector(n,12);  

if rising_edge(clk_plstr)then 

count<= count+'1'; 

end if; 

if(count<=pls)then  

if(clk_plstr'event and clk_plstr = '1')then 

output<='0'; 

else 

output<='1'; 

end if; 

else 

output<='0';  

end if; 

if (plsrep='1')then 

count<=B"000000000000";  

end if; 

end process; 

fout<=output;  

 

 

It would be very helpful if anyone can point out the problem by which I am getting this error.  

I would really appreciate your help. 

 

Thank you
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14 Replies
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Valued Contributor III
8 Views

Re: Signal output cannot be synthesized, bad synchronous description.

Are you making a counter with synchronous reset? An possible code is: 

 

process(rst, clk_plstr) 

begin 

if(rst='1') then 

count_reg <= ( others => '0' ); 

elsif(clk_plstr'event and clk_plstr='1') then 

count_reg<=count_next; 

end if; 

end process; 

 

count_next <= ( others =>'0' ) when (plsrep='1') else 

count_reg+1; 

 

Do you need to generate plsrep too?
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Valued Contributor III
8 Views

Re: Signal output cannot be synthesized, bad synchronous description.

Hi bretulus, 

 

I had used the same logic to do this task. 

I dont need to generate plsrep but i need to output my clock pulse (clk_plstr in my code) until the counting reach to some value(pls in my code). 

The coding that I did for this is following: 

process(clk_plstr,plsrep) ---to reset counter 

begin  

if rising_edge(plsrep)then 

count_reg<= B"000000000000" ; 

elsif(clk_plstr'event and clk_plstr='1')then 

count_reg<=count_next; 

end if; 

if(clk_plstr'event and clk_plstr = '1')then 

if(count_reg<=pls )then 

output<='0'; 

else 

output<='1'; 

end if; 

else 

output<='0';  

end if; 

end process; 

count_next <=count_reg+'1' when(count_reg=B"000000000000" and plsrep='1') else 

count_reg when (count_reg=B"000000000000") else 

count_reg+'1' when (count_reg<pls)else 

B"000000000000"; 

fout<=output; -----output the clock clk_plstr 

 

This gives me the same error as: 

"Signal output cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release." 

 

I am not sure how I can perform this task. 

 

Thank you very much.
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Valued Contributor III
8 Views

Re: Signal output cannot be synthesized, bad synchronous description.

There are some lines in your that may cause problems: 

 

if rising_edge(plsrep)then 

count_reg<= B"000000000000" ; 

elsif(clk_plstr'event and clk_plstr='1')then 

count_reg<=count_next; 

end if; 

 

The rising_edge means that plsrep is used as a clock signal. In a synchronous system ( fpgas ) you have only one clock. You may try: 

 

if plsrep = '1' then 

count_reg<= B"000000000000" ; 

elsif(clk_plstr'event and clk_plstr='1')then 

count_reg<=count_next; 

end if; 

 

But plsrep in this code works like an asynchronous reset. So don't use reset in the register declaration: 

 

process(clk_plstr) 

begin 

if(clk_plstr'event and clk_plstr='1') then 

count_reg<=count_next; 

end if; 

end process; 

 

count_next <=count_reg+'1' when(count_reg=B"000000000000" and plsrep='1') else 

count_reg when (count_reg=B"000000000000") else 

count_reg+'1' when (count_reg<pls)else 

B"000000000000";
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Valued Contributor III
8 Views

Re: Signal output cannot be synthesized, bad synchronous description.

Hi, 

I need to generate clk_plstr.
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Valued Contributor III
8 Views

Re: Signal output cannot be synthesized, bad synchronous description.

According to the codes you and me posted, clk_plstr should be the general clock of the system, so you don't need to generate it. You use it. But if you're trying to slow down the general clock you have to use a clock enable scheme. Give more details of your design.

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Valued Contributor III
8 Views

Re: Signal output cannot be synthesized, bad synchronous description.

Hi bretelus , 

Thank you for the sugesstion.It works if I used plsrep='1'. 

But when I try to output the clock pulse(clk_plstr here) then I again get the same error as: 

"Signal output cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release." 

 

 

The code to output this clock pluse looks like following: 

process(clk_plstr) 

begin 

.......... 

 

if(clk_plstr'event and clk_plstr = '1')then ----xst error to output like this? 

if(count_reg<=pls )then 

output<='1'; 

else 

output<='0'; 

end if; 

end process; 

 

It would be very helpful if you could point out the problem that I am getting now.Thank you
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Valued Contributor III
8 Views

Re: Signal output cannot be synthesized, bad synchronous description.

For a start, XST is a Xilinx tool - this is an Altera forum (Xilinx's competitor). 

 

Anyway, the error cant be seen in the code you have posted, post the whole code.
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Valued Contributor III
8 Views

Re: Signal output cannot be synthesized, bad synchronous description.

Hi Tricky, 

I right now I am doing simulation only.So I was trying both software quartus and xilinx. 

Following is the code which I think is giving me this error: 

process(clk_plstr) 

begin 

if(clk_plstr'event and clk_plstr='1') then 

count_reg<=count_next; 

if(count_reg<=pls )then 

output<='1'; 

else 

output<='0'; 

end if; 

end if; 

end process; 

count_next <=count_reg+'1' when(count_reg=B"000" and plsrep='1') else 

count_reg when (count_reg=B"000") else 

count_reg+'1' when (count_reg<pls)else 

B"000"; 

fout<=output; 

 

Thank you
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Valued Contributor III
8 Views

Re: Signal output cannot be synthesized, bad synchronous description.

That wont have errors. Post the whole code.

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Valued Contributor III
8 Views

Re: Signal output cannot be synthesized, bad synchronous description.

Is clk_plstr a real clock? or a logic generated clock?

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Valued Contributor III
8 Views

Re: Signal output cannot be synthesized, bad synchronous description.

Hi, 

This is the whole code which I am working right now: 

process(clk_plstr,plsrep) 

begin 

if(plsrep='1')then 

count_reg<=B"000"; 

end if;  

if(clk_plstr'event and clk_plstr='1') then 

count_reg<=count_next; 

if(count_reg<=pls )then 

output<='1'; 

else 

output<='0'; 

end if; 

end if; 

end process; 

count_next <=count_reg+'1' when(count_reg=B"000" and plsrep='1') else 

count_reg when (count_reg=B"000") else 

count_reg+'1' when (count_reg<pls)else 

--count_reg; 

B"000"; 

fout<=output; 

end Behavioral_plstr; 

 

It might be I have done some silly mistake. 

Thank you.
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Valued Contributor III
8 Views

Re: Signal output cannot be synthesized, bad synchronous description.

Well, you should have clk_plstr as an elsif to the plsrep. With the current code the plsrep is NOT a reset, as the clk gets priority over the reset. You should also assign output in the async reset part, or it will use the plsrep as a synchronous enable. 

 

And this still doesnt show the source of clk_plstr like I asked.
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Valued Contributor III
8 Views

Re: Signal output cannot be synthesized, bad synchronous description.

Missing elsif makes the "bad synchronous description".  

Clock source is interesting related to timing analysis but doen't affect the synthesis of the shown code.
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Valued Contributor III
8 Views

Re: Signal output cannot be synthesized, bad synchronous description.

Hi, 

I had made some small mistake and I figured it out. 

Thank you bertulus and tricky for explanation.
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