Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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SignalTap II Logic Analyzer

Altera_Forum
Honored Contributor II
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I am currently having trouble acquiring all of the input data using the SignalTap Logic Analyzer. It seems to only store half of the expected data (about 700 data points versus 1400+ data points) per waveform. We are using a variable k-clock which activates the data acquisition, and there are approximately 1400 cycles per waveform, so it should be getting that many data points. I tried changing the sample depth as well as the storage qualifier type, however we only saw a decrease in data quality. I was thinking we might change the trigger condition to an ‘or’ instead of ‘and.’ Does anyone have a suggestions as to how we should proceed?

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