Signaltap Effects Design Operation!

[Altera_Forum]

I am working on a design in Verilog. The design works normally with signaltap enabled. But, when I disable signaltap, the operation of the circuit changes. The results become erroneous. I think signaltap is an observer only, so it shouldn't change the design operation.  

 Does anyone have an idea about this problem?

[Altera_Forum]

--- Quote Start ---  I am working on a design in Verilog. The design works normally without signaltap enabled. But, when I enable signaltap, the operation of the circuit changes. The results become erroneous. I think signaltap is an observer only, so it shouldn't change the design operation. Am I doing sth wrong?   Does anyone have an idea about this problem?  --- Quote End ---    Hi,  yes Signaltap is an "observer", but it has an influence to the synthesis, routing and placement. Did you get new timing violation when you use signaltap ?  Kind regards  GPK

[Altera_Forum]

Hi pletz, 

 I've edit my post. Actually I mean the reverse. Design works normally with Signaltap enabled. When I disable it, the problems occur.   I use classic timing analyzer and there are no timing violations reported.   I use 2 clocks in the design (50M and 200MHz). Is there anything I should consider in multiclock case?   If you need to know any other information please ask me.   Thanks for your help.

[Altera_Forum]

The classical timing analyzer can't see all possible timing violations, particularly with multiple timing domains.

[Altera_Forum]

--- Quote Start ---  The classical timing analyzer can't see all possible timing violations, particularly with multiple timing domains.  --- Quote End ---     Thank you for your help Frank. You were right, Timequest solved some of my problems.    But I am new to timequest, so I don't really know how I can define all the constraints. I constrained only the main clock and PLL clocks for now. I guess the remaining problems are caused by undefined constraints. I use DE2-70 board and I am not sure about what the timing values should be set.    Is there any predetermined constraint values I can use or how can I determine them?

[Altera_Forum]

for the I/O, you should be able to take the constraints from a properly constrained example design and use them (with modified names) in your project. for internal logic, you will need to write your own constraints

[Altera_Forum]

--- Quote Start ---  for the I/O, you should be able to take the constraints from a properly constrained example design and use them (with modified names) in your project. for internal logic, you will need to write your own constraints  --- Quote End ---       Unfortunately, the design examples all utilize Classic TA and there is no SDC file given. This sounds strange but Altera uses classic TA in reference designs although they suggest using Timequest.   Anyway, in fact the most critical external part is the SSRAM in the design.  Do you have any idea on how to determine the constraints for SSRAM?   Thanks for your help..

[Altera_Forum]

ah, good point. 

 i think SSRAM should be fairly straight forward. you'll want to find the datasheet for the RAM, and maybe use another kit's constraints as an example (along with the TimeQuest documentation). here's the constraint from the CIII NEEK kit:  ##SSRAM Constraints set_output_delay -clock -reference_pin 2.4 set_input_delay -clock -reference_pin 4.1 set_multicycle_path -from -setup -end 2

[Altera_Forum]

Unbelieveable! Thank you very much "thepancake". I adapted your suggestions to my design and Timequest solved all the design problems.  

 Maybe not very important but one more thing is, when I write these constraints:    set_output_delay -clock { PLL_200MHz_inst|altpll_component|pll|clk } -reference_pin 2.4 set_input_delay -clock { PLL_200MHz_inst|altpll_component|pll|clk } -reference_pin 4.1    Timequest gives this warning:    Warning: Assignment: 'set_input_delay -add_delay -clock }] -reference_pin 4.100 ' had some problems but was accepted Warning: Set_input_delay/set_output_delay has replaced one or more delays on port "SRAM_DQ". Please use -add_delay option.    Do you suggest using add_delay option or is it fine as the one in your example?   Thanks again for your help..

[Altera_Forum]

i've been told it doesn't hurt to always include -add_delay to your set_input/output_delay constraints. you might want to check the TQ manual to see how this option is articulated