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Hello,
i've read this page: http://www.altera.com/support/examples/on-chip-debugging/signal-tap/signaltap2-design-examples.html and the Handbook. But I've still two questions. When is a flag or a counter updated, if I set a flag or e.g. increment a counter. Is the behavior like a variable or like a signal in VHDL. Combinational or Clocked? Can I use start_store stop_store as a Storage Qualifier? like this, it should store two samples, which can be in two ore more clock cyclesstate DStore:
begin
if (condValid)
begin
start_store;
stop_store;
set iq;
if (iq) //store I and Q sample
begin
goto SkipWords;
clear iq;
end
// set iq;
end
end
Thank you! Best regards Malte
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I find it just easier to add detection logic in your RTL. Then you know for sure when odd conditions over several clock cycles have occured.
You can use the syn_keep attributes on registers so you can then connect them to signaltap.
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