Simple problem with clock generation

[Altera_Forum]

Hi there, 

 I am experiencing an apparently simple, but frustating problem: when I generate a clock signal with a process that shows an empty sensitivity list, modelsim simulation returns an undefined value for the logical level that has not been initialized. However, compilation runs without any error or warning. Here's the code:  library ieee;use ieee.std_logic_1164.all; use ieee.numeric_std.all;   entity tb_test is end entity tb_test;   architecture tb of tb_test is   signal clk : std_logic;   constant clk_period : time := 10 ns;   begin   clk <= '1';   process  begin wait for clk_period/2; clk <= '0'; wait for clk_period/2; clk <= '1'; end process;    end tb;  I will attach a picture to show the behaviour of the signal clk during simulation. Thank you very much in advance for any hint.

[Altera_Forum]

you first set clock outside the process to'1', then start assigning values inside the process. You now have multiple drivers on the same signal. What is the level if a line is both connected to '1' and '0'? And for '1' and '1'? This is what you see. The syntax is correct, so the compilation for simulation will pass, I think that, should you do a similar thing for synthesis you'll find you get a multiple driver error. 

 And for the next time, please post your code between code tags.

[Altera_Forum]

Thank you!  

I fixed it and now it works. I'll make sure to use code tags next time, thank you!