Simplified Equation

[Altera_Forum]

Hello Folks, 

First time poster, I am using Altera Quartus 2 ver. 9.1. I have created a simple combinational logic circuit where the Boolean expression simplifies to a single input. I wanted to view the simplified Boolean expression that is listed in my book under floor plan view. When compilation occurs I am getting warnings that 2 of my pins are redundant, however I cannot view the simplified expression anywhere. Could someone please offer some advice? I am using MAX7000S family, targeting the EPM7128SCL84-10. The Boolean expression for the circuit I entered is: A’BC’+ABC’+A’BC+ABC. This will simplify to B. Thank you for your time.

[Altera_Forum]

Well if it simplifies to B, the synthesisor just strips out A and C so the input just connects to the output. The synthesisor always minimises logic to save space. Why would you want redundant logic. 

 You'll have to stick in an equation that doesnt reduce.

[Altera_Forum]

Thanks for the quick reply, I just wanted to see the simplified expression in Quartus 2 in floor plan view. The floor plan view does not support MAX7000S for some reason. It suggests I go to Timing Closure Floorplan, however I get no info there.

[Altera_Forum]

It's true, some Quartus features don't work for CPLD synthesis. But I still don't understand the exact problem. The logic can be minimized by pencil and paper method, so there' won't be doubts about the result. The implementation for Y = B should be clear without a floorplan, what are you missing? 

 You can however change the project to a FPGA target to evaluate logic minimization during synthesis.

[Altera_Forum]

FvM, 

I can fully appreciate the confusion regarding my question. There is no problem reducing using Boolean algebra or Karnaugh Maps. Its just something I wanted to see the software show it, just because the book I am reading stating Quartus could do it. You have answered my question, all I have to do is change to FPGA. Thank you very much.

[Altera_Forum]

One of the synthesisor's job is to do logic reduction. It doesnt really show how it does it, it just does it and gives you the result.

[Altera_Forum]

Thanks Tricky, I thought there may have been a way to view it in the package, however if there is not then my answer is fully answered. Thanks for your time.