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Altera_Forum
Honored Contributor I
1,227 Views

Simulating QSYS design with a DDR3 controller

Hi, 

 

I am having problems simulating a QSYS design with a DDR3 controller with UniPHY. 

I try to run a simulation by running the generated msim_setup.tcl. Compilation works as expected, but when i run "elab" the loading fails: 

 

# ** Fatal: Error occurred in protected context. # Time: 0 ps Iteration: 0 Instance: /top/mem_if_ddr3_emif_0/c0/ng0/alt_mem_ddrx_controller_top_inst/controller_inst/rdata_path_inst/gen_rdata_return_inorder/genblk1/in_order_buffer_inst File: nofile # FATAL ERROR while loading design # Error loading design 

 

If I remove the DDR3 controller from the design it loads with no errors. 

Does anyone know why this error occurs and how to avoid it? 

 

The design is generated in Quartus II 11.0sp1 with VHDL simulation model generation selected. I am running ModelSim PE 6.6d for simulation.
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7 Replies
Altera_Forum
Honored Contributor I
50 Views

Hi, 

 

I have the same problem, with a design that only contains a DDR2 controller with uniphy. I also used the generated msim_setup.tcl. Won't get it working.
Altera_Forum
Honored Contributor I
50 Views

I have tried without our custom Avalon-MM compliant cache (see this issue http://www.alteraforum.com/forum/showthread.php?t=32304 ) and the complete system in Verilog and it works, so I guess something is wrong with mixed-language designs. 

 

I will go back to sopc_builder now. We have paid much money for a mixed-language simulation license and we are VHDL guys, if we can't use the license now and lose even more time on the project because everybody has to learn Verilog the project is dead. 

 

I'm really p***ed off with that Qsys stuff by now.
Altera_Forum
Honored Contributor I
50 Views

I had problems with the mixed language stuff also... i had to change altera's source code instantiation in verilog...

Altera_Forum
Honored Contributor I
50 Views

I also guess it has something to do with instantiation of VHDL stuff in the generated Verilog files. But the files are encrypted, I have no idea how to change this. We thought about implementing Verilog wrappers for all our components - I guess that would match the Qsys philosophy perfectly :o . Maybe it is the simplest solution for the problem with this very component but in the end we will spend time working around language problems, so I am not convinced. We have done two projects with sopc_builder where everything worked out alright so why change? If qsys on the other hand lacks proper mixed-language support we will never be happy with it.

Altera_Forum
Honored Contributor I
50 Views

Flintstone then keep your design in SOPC until QSys is more solid i guess

Altera_Forum
Honored Contributor I
50 Views

I tried going back to sopc_builder but it failed with identical symptoms. I think the problem is related to the Uniphy but I do not know. 

 

We tried with Quartus II versions 11.0, 11.0SP1 and 11.1 and couldn't get it working. We really have a problem by now. 

 

Since the last project was successfully done with the DDR2 interface with altmemphy I would like to give this one a try but when I inserted into the Qsys system I could not find a memory model that's accepted, there always was an error that the memory model is only supported by the Uniphy DDR2 interface. Am I doing something wrong or can the altmemphy interface not be used with Qsys? 

 

Best regards, 

flintstone
Altera_Forum
Honored Contributor I
50 Views

 

--- Quote Start ---  

Hi, 

 

I am having problems simulating a QSYS design with a DDR3 controller with UniPHY. 

I try to run a simulation by running the generated msim_setup.tcl. Compilation works as expected, but when i run "elab" the loading fails: 

 

# ** Fatal: Error occurred in protected context.# Time: 0 ps Iteration: 0 Instance: /top/mem_if_ddr3_emif_0/c0/ng0/alt_mem_ddrx_controller_top_inst/controller_inst/rdata_path_inst/gen_rdata_return_inorder/genblk1/in_order_buffer_inst File: nofile# FATAL ERROR while loading design# Error loading design 

 

If I remove the DDR3 controller from the design it loads with no errors. 

Does anyone know why this error occurs and how to avoid it? 

 

The design is generated in Quartus II 11.0sp1 with VHDL simulation model generation selected. I am running ModelSim PE 6.6d for simulation. 

--- Quote End ---  

 

 

 

The solution: After you get this no file/error in protected context in ModelSim's transcript window, go to Modelsim's main window under Tools/Tcl/Execute Macro search for the folder named <component_name>_sim/mentor and select and run the file msim_setup.tcl. Where I have assumed your instance of the megacore is <component_name>. Then, run a .do file from the modelsim transcript which only compiles your design files (not the libraries or megafunction related files) from modelsim's transcript window. You can cut and paste it into the transcript from the bottom half of the .do which created the error in the first place including the vsim, wave and run -all lines. 

 

Apparently, there are things in the .tcl which must be used to setup modelsim before it can load all files for a certain megacores, including certain high speed phy cores like XAUI. Actually, this is vaguely inferred from table 1-5 of Altera's "Simulating Altera Designs": in www dot altera dot com/literature/hb/qts/qts_qii53025.pdf. Unfortunately, Altera did not post it as a work-around on page 15 of www dot altera dot com/literature/rn/archives/rn_qts_110sp1.pdf, where they list this as an issue for low latency phy megafunctions with 10 Gps data paths. I had this same error for a XAUI PHY. My guess is that Altera builds their interoperability fixes with various simulation tools into their .tcl setup files for those tools. It is wise to try to use them to try and resolve these issues.
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