Simulating VHDL test bench using Modelsim

[Altera_Forum]

can anyone tell me the steps to follow in order to simulate my vhdl test bench with modelsim-altera? I had type my test bench with Quartus II and save the file.

[Altera_Forum]

1. Create your waveform vector file in Quartus II 

2. Export this file to vhdl test bench (file->export) 3. Click, asssigments->settings->EDA tool settings->Simulation , choose modelsim altera.  chooose compile test bench in native link settings panel, click test benches, click new,     chosse any name for test bench, in test bench entity write: <your_top_level_entity>vhd_vec_tst  in instance name write : i1  chosee the file generated in step 1 in test bench files.  3. Compile your project.  4. click, tools->eda simulation tools: run eda rtl simulation for functional simulation or run eda gate level simulation for timing simulation.  After this steps quartus ii opens modelsim an starts the simulation.

[Altera_Forum]

thx for the replay. I can simulate the test bench already but when i want to view the waveform in wave window on modelsim, the wave windows appear but is blank didn't have anythings at all... what I should do to view the simulation on the waveform windows?

[Altera_Forum]

I get the following message in the transcript panel: 

# Invalid time string specified: # Could not find Wave window Invalid time string specified:

[Altera_Forum]

Did you export the .vwf file into .vht ?

[Altera_Forum]

No. I didn't export anythings. can you tell me what I have to do inorder set the wave window to the default setting? thx file:///C:/DOCUME%7E1/XP/LOCALS%7E1/Temp/moz-screenshot-3.jpg

[Altera_Forum]

The image link is dead

[Altera_Forum]

Sorry. I have attach the pictures. the 1st picture is the view of the wave window. the 2nd one is the view of wave window preferences. It is disable. so I think I maybe some how have changes the setting of the software so causing the wave windows didn't show anythings. how to restore the default setting of the modelsim? I reinstall the modelsim but the problem still occur...

[Altera_Forum]

please post your test bench file and your .vwf file

[Altera_Forum]

here is my test bench : 

  LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE WORK.pipeline_package.ALL;  ENTITY register_file_tb_ent IS END register_file_tb_ent;  ARCHITECTURE register_file_tb_arch OF register_file_tb_ent IS  COMPONENT register_file_ent PORT(   pd_read: IN std_logic;  pd_source1: IN register_type;  pd_source2: IN register_type;  clock: IN std_logic;  flush: IN std_logic;  ex_store: IN std_logic;  ex_destination: IN register_type;  ex_data: IN std_logic_vector(31 downto 0);  source1_data: OUT std_logic_vector(31 downto 0);  source2_data: OUT std_logic_vector(31 downto 0)  ); END COMPONENT;  SIGNAL pd_read: std_logic; SIGNAL pd_source1: register_type; SIGNAL pd_source2: register_type; SIGNAL clock: std_logic:= '0'; SIGNAL flush: std_logic; SIGNAL ex_store: std_logic; SIGNAL ex_destination: register_type; SIGNAL ex_data: std_logic_vector(31 downto 0); SIGNAL source1_data: std_logic_vector(31 downto 0); SIGNAL source2_data: std_logic_vector(31 downto 0);  CONSTANT CYCLE : TIME := 50 us;  BEGIN  DUT: register_file_ent port map( pd_read, pd_source1, pd_source2, clock, flush, ex_store, ex_destination, ex_data, source1_data, source2_data);  clock <= NOT clock AFTER CYCLE/2;  PROCESS BEGIN  flush <= '0'; pd_read <= '0'; pd_source1 <= reg0; pd_source2 <= reg0; ex_store <= '0'; ex_destination <= reg0; ex_data <= ZERO; wait for CYCLE;  ex_store <= '1'; ex_destination <= reg0; ex_data <= "00000000000000010000000001010001"; wait for CYCLE;  ex_store <= '1'; ex_destination <= reg1; ex_data <= "00000000000000000000000000000001"; wait for CYCLE;  ex_store <= '0'; pd_read <= '1'; pd_source1 <= reg0; pd_source2 <= reg1; wait for CYCLE;  ex_store <= '0'; pd_read <= '1'; pd_source1 <= reg0; pd_source2 <= reg1; wait for CYCLE;  END PROCESS; END register_file_tb_arch;  CONFIGURATION register_file_tb_config OF register_file_tb_ent IS   FOR register_file_tb_arch  FOR ALL : register_file_ent  USE ENTITY WORK.register_file_ent(register_file_arch);  END FOR;  END FOR; END register_file_tb_config;   What is a .vwf file? I can not find it at the source folder. is it generate automatically when we compile the vhdl file?

[Altera_Forum]

--- Quote Start ---  I get the following message in the transcript panel:  # Invalid time string specified: # Could not find Wave window Invalid time string specified:  --- Quote End ---     I did have excatly the same problem just like yours. I am using ACTEL Libero and ModelSim Actel to do the wave simulation   the thing is, as soon as I open the ModelSim, after some compiling, there is always an error message appeared on the transcript window:# invalid time string specified  then the wave window is just blank   can someone here tell me whats going on with the software?:(

[Altera_Forum]

please keep discussion to Altera related products on the Altera Forum 

 thanks

[Altera_Forum]

--- Quote Start ---  1. Create your waveform vector file in Quartus II 2. Export this file to vhdl test bench (file->export) 3. Click, asssigments->settings->EDA tool settings->Simulation , choose modelsim altera.  chooose compile test bench in native link settings panel, click test benches, click new,     chosse any name for test bench, in test bench entity write: <your_top_level_entity>vhd_vec_tst  in instance name write : i1  chosee the file generated in step 1 in test bench files.  3. Compile your project.  4. click, tools->eda simulation tools: run eda rtl simulation for functional simulation or run eda gate level simulation for timing simulation.  After this steps quartus ii opens modelsim an starts the simulation.  --- Quote End ---    I do step by step follow your introduction. When I run eda rtl simulation or functional simulation, I met a lot of problem:  This is error:  Error: Compilation of design file Counter.vho was NOT successful Error: ModelSim: Model Technology ModelSim SE vcom 5.7d Compiler 2003.05 May 10 2003 Error: ModelSim: -- Loading package standard Error: ModelSim: ** Error: (vcom-19) Failed to access library 'cycloneii' at "C:/Modeltech_5.7d/win32/../altera/vhdl/cycloneii". Error: ModelSim: No such file or directory. (errno = ENOENT) Error: ModelSim: ** Error: Counter.vho(29): Library cycloneii not found. Error: ModelSim: -- Loading package std_logic_1164 Error: ModelSim: ** Error: Counter.vho(31): Unknown identifier: cycloneii Error: ModelSim: ** Error: Counter.vho(33): VHDL Compiler exiting Error: ModelSim: child process exited abnormally Error: NativeLink simulation flow was NOT successful Error: For messages from NativeLink scripts, check the file D:/Quartus_code/Quartus5/Countertest/quartus_nativelink_simulation.log   This is log file:  Info: Start Nativelink Simulation process Info: Initialization of EDA simulation settings was successful ========= EDA Simulation Settings ===================== Family : CYCLONEII Quartus root : c:/altera/quartus50/bin/ Quartus sim root : c:/altera/quartus50/bin/../eda/sim_lib Simulation Tool : modelsim-altera Simulation Language : vhdl Version : 87 Sim Output File : Counter.vho Sim SDF file : Counter_vhd.sdo Sim dir : simulation\modelsim ======================================================= Info: Changed to directory simulation\modelsim ... Info: Current directory is : D:/Quartus_code/Quartus5/Countertest/simulation/modelsim Info: Running ModelSim-Altera software Info: VHDL script : c:/altera/quartus50/bin//modelsim_vhdl.tcl Info: Initialization of NativeLink successful Info: Initialization of EDA advanced simulation settings was successful Info: Creating directory modelsim_work for VHDL simulation Info: Compiling design file Counter.vho Error: Compilation of design file Counter.vho was NOT successful ModelSim: Model Technology ModelSim SE vcom 5.7d Compiler 2003.05 May 10 2003 ModelSim: -- Loading package standard ModelSim: ** Error: (vcom-19) Failed to access library 'cycloneii' at "C:/Modeltech_5.7d/win32/../altera/vhdl/cycloneii". ModelSim: No such file or directory. (errno = ENOENT) ModelSim: ** Error: Counter.vho(29): Library cycloneii not found. ModelSim: -- Loading package std_logic_1164 ModelSim: ** Error: Counter.vho(31): Unknown identifier: cycloneii ModelSim: ** Error: Counter.vho(33): VHDL Compiler exiting ModelSim: child process exited abnormally Error: NativeLink simulation flow was NOT successful ================The following additional information is provided to help identify the cause of error while running nativelink scripts================= Nativelink TCL script failed with errorCode: CHILDSTATUS 3836 2 Nativelink TCL script failed with errorInfo: Model Technology ModelSim SE vcom 5.7d Compiler 2003.05 May 10 2003 -- Loading package standard ** Error: (vcom-19) Failed to access library 'cycloneii' at "C:/Modeltech_5.7d/win32/../altera/vhdl/cycloneii". No such file or directory. (errno = ENOENT) ** Error: Counter.vho(29): Library cycloneii not found. -- Loading package std_logic_1164 ** Error: Counter.vho(31): Unknown identifier: cycloneii ** Error: Counter.vho(33): VHDL Compiler exiting child process exited abnormally while executing "exec vcom $cmp_opts -work modelsim_work $src "   This is my code (just a simple counter up)  library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; entity counter is port (result : out std_logic_vector(7 downto 0); clk : in bit; reset : in bit); end; architecture only of counter is signal count : std_logic_vector(7 downto 0); begin process(clk,reset,count) begin if (reset ='1') then count <= x"00"; elsif clk'event and clk = '1' then count <= count + '1'; end if; result<=count; end process; end only;   and EDA setting I attached in this post. Could you help me solve this problem. thank you very much best regards

[Altera_Forum]

And when I compile this vhdl code in modelsim. I met this problem. Can you help me solve it? thank you very much.

[Altera_Forum]

use unsigned type for your count and assign initial value. 

signal count : unsigned(7 downto 0) := x"00";  use count + 1 instead of count + '1'; result <= std_logic_vector(count);  by the way your code infers extra 8 registers unneccessarily

[Altera_Forum]

Thank you very much. I try it now.

[Altera_Forum]

Try numeric_std library instead of std_logic_signed.

[Altera_Forum]

--- Quote Start ---  Try numeric_std library instead of std_logic_signed.  --- Quote End ---   I'm sorry. if you use "unsigned(7 downto 0) := x"00"". You can not use numeric_std. It will be error when you compile in Quartus. Please help me

[Altera_Forum]

Have you deleted both packages std_logic_arith and std_logic_signed from your code? 

 unsigned(7 downto 0) := x"00" is perfectly legal code with numeric_std.

[Altera_Forum]

--- Quote Start ---  Have you deleted both packages std_logic_arith and std_logic_signed from your code?  unsigned(7 downto 0) := x"00" is perfectly legal code with numeric_std.  --- Quote End ---    I'm sorry. I made a mistake. I had checked it.  I do with QuartusII version 5.0 and Modelsim SE PLUS 5.7d. With QuartusII it is ok. But with Modelsim it still has error. I send this file to you and hope you help me to solve this problem. Thank you very much   This is the error it notice me in Modelsim    --- Quote Start ---   # do Counter_run.do  # vsim -sdftyp /i1=Counter_vhd.sdo work.<counter>vhd_vec_tst  # ** Error: (vsim-3170) Could not find 'modelsim_work.work.<counter>vhd_vec_tst'. # Error loading design # Error: Error loading design  # Pausing macro execution  # MACRO ./Counter_run.do PAUSED at line 1     --- Quote End ---  

[Altera_Forum]

modify the counter_run.do to: 

 vsim -sdftyp /i1=Counter_vhd.sdo work.counter_vhd_vec_tst add wave * run 100ns  if this file is auto-generated, there is a problem somewhere in the auto-generation.