Simulating communication over PCIE

[lucadimauro]

Hello,
I'm trying to perform some tests regarding simulation of the communication between an FPGA and an host PC over a PCIE bus. To simulate the FPGA I use ModelSim-Altera and Quartus II Lite Edition and Xillybus library to perform such communication.
I downloaded the Xillybus demo an synthetized succesfully, but I still don't see any /dev/xillybus_something device file.

I do these tests with the university, so I cannot buy yet an FPGA and my PC doesn't have a PCIE port natively.
I use Ubuntu 20.04 as host OS.

Is it reasonable to do such test? Can you provide me some tips on how to simulate such communication?

Thank you very much for your support.

[SengKok_L_Intel]

Hi,

Assuming you are targeting Arria 10 device, the simulator that supported is listed in Table 9 from the link below.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avst.pdf

For your information, we don’t work on the Xillybus tool, so I afraid no much support can offer here.  

Regards -SK

[lucadimauro]

Hi,

thank you for your reply SengKok.

What I'm asking is to know if I can simulate a PCIE block file on the host system connected to the simulated FPGA with vsim tool. But I think that it is not possible.

Regards,

Luca

[SengKok_L_Intel · Accepted solution]

Hi Luca,

Yes, I don't think this is feasible. The existing PCIe generated testbench and BFM provides a simple method to do basic testing of the application layer logic, and this is not intended to be a substitute for a full verification environment.

[lucadimauro]

Hi SengKok,

ok, I understood the problem. I'll try to buy a suitable dev board.

Thank you.

Regards,

Luca

[SengKok_L_Intel]

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