Hello,
I have written a design composed of multiple instances - I included an example of block scheme, it's not quite exactly what I did in the end, but similar. I then used the testbench generator in Quartus and wrote a testbench that defines input signals for top module (osnutekptp), that is, clk, count, and data. I expected the input to work its way through whole design, wherever signals with the same name and mode 'in' show up. However, when I simulate it, it's clear that only top module that I explicitly wrote testbench for got the signals - there is a screenshot from ModelSim below. Do I have to write additional testbenches for the rest of the modules, or how do I go about simulating such a design? Or, does that mean there are errors in my design to begin with, such as faulty port maps or something?
Thanks in advance.
https://www.alteraforum.com/forum/attachment.php?attachmentid=6871 https://www.alteraforum.com/forum/attachment.php?attachmentid=6872 https://www.alteraforum.com/forum/attachment.php?attachmentid=6873
