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Simulation Error

Altera_Forum
Honored Contributor II
‎04-15-2011 02:09 PM
1,370 Views

Hi, all: 

I encoutered a problem --- when I do RTL simualtion, it shows a warning: 

 

Warning : Invalid transition to 'X' detected on PLL input clk. This edge will be ignored. 

Time: 0 Instance: Test_vlg_vec_tst.i1.ClkConv.altpll_component.pll0.n1 

Error: (vsim-3601) Iteration limit reached at time 0 ps. 

 

I just have an initial block to simulate the external clock input. So what's the problem. Please give me some clues. Thank you very much!
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Altera_Forum
Honored Contributor II
‎04-26-2011 06:44 AM
666 Views

Check that you don't have two sources for the pll input clock, such as two different processes.

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Altera_Forum
Honored Contributor II
‎04-26-2011 09:37 AM
666 Views

Hi, Daixiwen: 

 

Thanks for the reply. I found the error was caused by the unit of timescale. I change 1ps to 1ns, and the error vanished.
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