heey all,
i've done writing a vhdl code on Quartus || but i faced this problem
when i simulate in functional simulation mode, the circuit is doing well and the output comes as it's expected!
but when simulating the whole code on Timing mode, the circuit seems not to function correctly and the output is wrong for the same input of the above iteration!
if the problem is due to delay, please tell me how can i solve it
and will i face problems when downloading the code on FPGA ?
...
Thanks in advance!
