I have used Quartus II 14.1 (64-bit version).I made a mod 3 asynchronous counter as Fig 1. The functional simulation issues the error message as Fig 2. And, the timing simulation result is weird. I expect the result sequence is 00->01>10->(temporally 11)->00->01->........ But, the result is weird as Fig3. Is this a simulator bug? Or, let me know what is a part of mistake. Th higher version of Quartus II 14 is as the same. Thanks, Ed
Iteration limits occur when you have a logic loop that cause the system to oscillate in 0 time. It's probably something to do with the loop cause by the resets
I understand why the error has occurred.However as to the solution, I am unsure which parts must be altered or modified in order for the simulator to perform correctly like an actual circuit. Actual circuit is working correctly.